# FP6381AS5CTR

**Fitipower Integrated Tech** · DC-DC Converters · SOT-23-5

FP6381AS5CTR from Fitipower Integrated Tech, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Enable control pin. Pull high (VIH >= 1.5V) to turn the IC on, pull low (VIL <= 0.4V) to disable. Must not be left floating. |
| 2 | GND | power_in | Ground pin. Power return for the internal N-channel low-side MOSFET and control circuitry. |
| 3 | LX | output | Power switching output node. Connect the external inductor between LX and the output filter capacitor. Rated to VIN+0.3V max. Internal 100Ω discharge resistance when disabled. |
| 4 | VIN | power_in | Power supply input pin, 2.5V to 6V operating range (6.5V absolute max). Place input decoupling capacitor (e.g. 4.7µF MLCC) as close as possible from VIN to GND to minimize noise. |
| 5 | FB | input | Voltage feedback input pin. Connect FB to VOUT through a resistive divider; the internal error amplifier regulates FB to VREF = 0.6V (typ, 0.588V-0.612V). Input leakage <= 1µA. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Fitipower Integrated Tech |
| Package | SOT-23-5 |
| Category | PMIC |
| Pins | 5 |

## Ordering variants

Same part, different packaging or reel option.

- `FP6381AS5CTR`
- `FP6381AS5CTRS6CTR`
- `FP6381AS5CTRS8CTR`

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Reference Voltage | VREF | 0.588 | 0.6 | 0.612 | V |  | 5 |
| Oscillation Frequency | FOSC | 1.2 | 1.5 | 1.8 | MHz | IOUT=200mA | 5 |
| Shutdown Current | ISHDN |  | 0.1 | 1 | μA | EN=0V | 5 |
| FB Input Leakage Current | IFB |  | 0.01 | 1 | µA | VFB=VIN | 5 |
| Supply Voltage (VIN) | VIN | 2.5 |  | 6 | V |  | 4 |
| Operation Temperature Range | TOPR | -40 |  | 85 | °C |  | 4 |
| VIN to GND | VIN | -0.3 |  | 6.5 | V |  | 4 |
| LX to GND |  | -0.3 |  |  | V |  | 4 |
| EN, FB, PG to GND |  | -0.3 |  |  | V |  | 4 |
| Storage Temperature | TS | -65 |  | 150 | °C |  | 4 |
| Maximum Junction Temperature | TJ |  |  | 150 | °C |  | 4 |
| Lead Temperature (Soldering) |  |  |  | 260 | °C | Soldering, 10 sec | 4 |
| Package Thermal Resistance SOT-23-5 (junction-to-ambient) | θJA |  | 250 |  | °C/W | SOT-23-5 | 4 |
| Package Thermal Resistance SOT-23-5 (junction-to-case) | θJC |  | 130 |  | °C/W | SOT-23-5 | 4 |
| Quiescent Current | Iq |  | 80 |  | μA | VFB=0.65V, IOUT=0A | 5 |
| P-Channel MOSFET On-Resistance | RDS(ON) |  | 300 |  | mΩ | Note 3 | 5 |
| N-Channel MOSFET On-Resistance | RDS(ON) |  | 250 |  | mΩ | Note 3 | 5 |
| P-Channel Current Limit | ILIM |  | 1.6 |  | A | Note 3 | 5 |
| EN High-Level Input Voltage | VIH |  | 1.5 |  | V |  | 5 |
| EN Low-Level Input Voltage | VIL |  | 0.4 |  | V |  | 5 |
| Under Voltage Lockout Voltage | UVLO |  | 2.4 |  | V |  | 5 |
| UVLO Hysteresis | VHYS |  | 0.2 |  | V |  | 5 |
| Minimum On Time |  |  | 50 |  | ns |  | 5 |
| Maximum Duty Cycle |  |  | 100 |  | % |  | 5 |
| Internal Soft Start Time | TSS |  | 1 |  | ms |  | 5 |
| PG Rising Threshold | VPG(H) |  | 90 |  | % | VFB Rising | 5 |
| PG Sink Current | IPG |  | 1 |  | mA | VPG=0.1V | 5 |
| LX Discharge Resistance |  |  | 100 |  | Ω |  | 5 |
| Thermal Shutdown Temperature | TSD |  | 150 |  | °C | Note 3 | 5 |

## CAD (KiCad official)

- Symbol: `FP6381AS5CTR`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files: `fp6381as5ctr-etched.step` / `fp6381as5ctr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `fp6381as5ctr.step` / `fp6381as5ctr.glb` are the bare package body.

## 3D model downloads

Two STEP files. Same geometry, different body top:

| File | Size | Use it when |
|---|---|---|
| [`fp6381as5ctr.step`](fp6381as5ctr.step) | 85 KB | You want the bare part, or you mark your own boards. |
| [`fp6381as5ctr-etched.step`](fp6381as5ctr-etched.step) | 2.4 MB | You want the part with `FP6381AS5CTR` already on it. |

The marking in the etched file is real recessed geometry cut into the solid, not a
texture or a decal: 582 faces against 102 in the bare model. It
survives export, section views, and rendering in any CAD tool, and it drops straight
into KiCad or Fusion with no extra setup.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Fitipower Integrated Tech datasheet](docs/fp6381as5ctr-datasheet.pdf) (15 pp, sha256 `4b3207bd5495340b`, retrieved 2026-08-17, tier: lcsc)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/fp6381as5ctr-datasheet.pdf)