component
FP6296XR-G1
Public Made by Adomby adom
Advanced Analog Technology DC-DC Converters, SOP-8-EP. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
FP6296XR-G1
Advanced Analog Technology · DC-DC Converters · SOP-8-EP
FP6296XR-G1 from Advanced Analog Technology, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LX | output | Power switch output. Drain of the internal 15 mΩ / 14 V / 10 A N-channel power MOSFET; connects to the boost inductor and Schottky diode anode. Pin 1 and pin 2 are tied together internally for higher current-carrying capability. |
| 2 | LX | output | Power switch output. Second LX pin bonded to the same internal MOSFET drain as pin 1; must be connected together on the PCB to carry the 10 A switch current. |
| 3 | Vcc | power_in | Power supply for the internal control circuitry and gate drivers. Regulated to ~5 V (4.75-5.25 V) internally from HVDD when HVDD = 12 V. Bypass to GND with a ceramic capacitor. |
| 4 | EN | input | Enable control input, active high. VEN ≥ 1.1 V enables the converter; VEN ≤ 0.6 V shuts it down (IDD ≤ 1 µA in shutdown). Do not leave floating. |
| 5 | FB | input | Error amplifier inverting input (feedback). Connect to a resistor divider from VOUT; regulates to the internal 1.2 V (±2%) reference (VREF = 1.176-1.224 V). |
| 6 | COMP | output | Loop compensation node. Error amplifier output; connect an R-C network to GND to stabilize the current-mode control loop. Sink/source capability ≈ 45 µA. |
| 7 | OC | input | Adjustable over-current limit programming pin. Connect a resistor (150 kΩ ↔ 51 kΩ) from OC to GND to set the peak current limit between 2 A and 10 A. Leaving this pin floating disables the adjustment (invalid); the default OCP is 10 A. |
| 8 | HVDD | power_in | IC power supply input, 2.7 V to 12 V (abs max 12 V). Provides bias for the internal LDO that generates VCC; also monitored by the UVLO circuit (VUVLO ≈ 2.2 V, 0.1 V hysteresis). |
| EP | GND | power_in | IC ground - exposed thermal pad on the bottom of the SOP-8L(EP) package. Must be soldered to the PCB ground plane for correct electrical operation and heat dissipation (θJC ≈ 10 °C/W, θJA ≈ 60 °C/W). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Advanced Analog Technology |
| Package | SOP-8-EP |
| Category | PMIC |
| Pins | 9 |
Ordering variants
Same part, different packaging or reel option.
FP6296XR-G1
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | HVDD | 0 | 12 | V | 5 | ||
| LX Voltage | VLX | 0 | 14 | V | 5 | ||
| Others Pin Voltage | 0 | 6 | V | 5 | |||
| Thermal Resistance (Junction to Ambient) | θJA | 60 | °C / W | 5 | |||
| Thermal Resistance (Junction to Case) | θJC | 10 | °C / W | 5 | |||
| Junction Temperature | TJ | 150 | °C | 5 | |||
| Operating Temperature | TOP | -25 | 85 | °C | 5 | ||
| Storage Temperature | TST | -65 | 150 | °C | 5 | ||
| Lead Temperature (soldering, 10 sec) | 260 | °C | soldering, 10 sec | 5 | |||
| Supply Voltage | HVDD | 2.7 | 12 | V | 6 | ||
| Operating Temperature Range | TA | -25 | 85 | °C | Ambient Temperature | 6 | |
| Input Supply Range | HVDD | 2.7 | 12 | V | 6 | ||
| Shutdown Supply Current | IDD | 1 | µA | VEN=GND | 6 | ||
| Input Supply Voltage | VCC | 4.75 | 5 | 5.25 | V | HVDD=12V, VCC no current | 6 |
| Operation Frequency | FOSC | 340 | 400 | 460 | KHZ | 6 | |
| Reference Voltage | VREF | 1.176 | 1.2 | 1.224 | V | 6 | |
| Adjustable OCP Current | IOCP | 2 | 10 | A | With External Resistor: 150k~51kΩ | 6 | |
| Under Voltage Lockout | VUVLO | 2.2 | V | 6 | |||
| UVLO Hysteresis | 0.1 | V | 6 | ||||
| Quiescent Current | IDD | 0.45 | mA | VFB=1.3V, No switching | 6 | ||
| Average Supply Current | IDD | 4 | mA | VFB=1.1V, Switching | 6 | ||
| Frequency Change with Voltage | △ f / △ V | 5 | % | HVDD=2.5V to 12V | 6 | ||
| Maximum Duty Cycle | TDUTY | 90 | % | 6 | |||
| Line Regulation | 0.2 | % / V | HVDD=2.5V～12V | 6 | |||
| COMP Pin Sink Current | ISINK | 45 | µA | 6 | |||
| COMP Pin Source Current | ISOURCE | 45 | µA | 6 | |||
| Enable Voltage | VEN | 1.1 | V | 6 | |||
| Shutdown Voltage | VEN | 0.6 | V | 6 | |||
| On Resistance of Driver | RDS(ON) | 15 | mΩ | VCC=5V, ILX=0.5A | 6 | ||
| OCP Current | IOCP | 10 | A | 6 | |||
| OTP Temperature | TOTP | 150 | °C | 6 |
CAD (KiCad official)
- Symbol:
FP6296XR-G1 - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOP-8-EP (KiCad packages3D, STEP)
- 3D model files:
fp6296xr-g1-etched.step/fp6296xr-g1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);fp6296xr-g1.step/fp6296xr-g1.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
fp6296xr-g1.step |
125 KB | You want the bare part, or you mark your own boards. |
fp6296xr-g1-etched.step |
2.3 MB | You want the part with FP6296XR-G1 already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 562 faces against 152 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Advanced Analog Technology datasheet (13 pp, sha256
a502d340a0d45551, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).