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FM25V05-GTR

Public Made by Adom

by adom

Infineon Cypress Semicon FRAM, SOIC-8. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.

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FM25V05-GTR

Infineon Cypress Semicon · FRAM · SOIC-8

FM25V05-GTR from Infineon Cypress Semicon, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 HOLD input Active-LOW input that suspends current memory operations; has weak internal pull-up (40 kΩ minimum) and must be tied to VDD if unused.
2 SCK input Serial clock input for synchronizing all I/O activity; accepts clock frequencies from 0 to 40 MHz with inputs latched on rising edge and outputs occurring on falling edge.
3 SI input Serial input pin for all data; sampled on rising edge of SCK and must be driven to valid logic level to meet IDD specifications.
4 SO tri_state Serial output pin for read data; driven on falling edge of SCK and tristated when HOLD is LOW or device is deselected.
5 VSS power_in Ground connection for device; must be connected to system ground.
6 WP input Active-LOW write protect input that prevents Status Register writes when WPEN bit is set to 1; must be tied to VDD if unused.
7 VDD power_in Power supply input; operating range 2.0 V to 3.6 V over industrial temperature range -40 °C to +85 °C.
8 CS input Active-LOW chip select input that activates device; device enters low-power standby mode and tristates output when CS is HIGH.

Key specifications

Parameter Value
Manufacturer Infineon Cypress Semicon
Package SOIC-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage temperature TSTG -55 125 °C 13
Ambient temperature with power applied TA -55 125 °C Power applied 13
Supply voltage on VDD relative to VSS VDD -1 4.5 V Relative to VSS 13
Input voltage VIN -1 4.5 V VIN < VDD + 1.0 V 13
DC voltage applied to outputs in High-Z state VOUT -0.5 V Outputs in High-Z state 13
Transient voltage on any pin to ground potential -2 V < 20 ns 13
DC output current IOUT 15 mA 1 output at a time, 1 s duration 13
Ambient operating temperature (industrial) TA -40 85 °C Industrial range 13
Thermal resistance junction to ambient (8-pin SOIC) JA 138 °C/W Per EIA/JESD51 14
Thermal resistance junction to case (8-pin SOIC) JC 40 °C/W 14
Power supply voltage VDD 2 3.3 3.6 V 13
VDD supply current IDD 0.3 mA SCK toggling between VDD, 0.2 V and VSS, other inputs VSS or VDD, 0.2 V; SO = Open; fSCK = 1 MHz 13
VDD supply current IDD 1.5 3 mA SCK toggling between VDD, 0.2 V and VSS, other inputs VSS or VDD, 0.2 V; SO = Open; fSCK = 40 MHz 13
VDD standby current ISB 90 150 µA CS = VDD; all other inputs VSS or VDD 13
Input leakage current (except HOLD pin) ILI -1 1 µA VSS < VIN < VDD 13
Output leakage current ILO -1 1 µA VSS < VOUT < VDD 13
Input LOW voltage VIL -0.3 V 13
Output HIGH voltage VOH1 2.4 V IOH = -1 mA, VDD = 2.7 V 13
Output LOW voltage VOL1 0.4 V IOL = 2 mA, VDD = 2.7 V 13
Output LOW voltage VOL2 0.2 V IOL = 150 µA 13
Input resistance (HOLD pin) RIN 40 kΩ For VIN = VIH(min) 13
Input resistance (HOLD pin) RIN 1 MΩ For VIN = VIL(max) 13
Data retention TDR 10 Years TA = 85 C 14
Data retention TDR 38 Years TA = 75 C 14
Data retention TDR 151 Years TA = 65 C 14
Output pin capacitance (SO) CO 8 pF TA = 25 C, f = 1 MHz, VDD = VDD(typ) 14
Input pin capacitance CI 6 pF 14
SCK clock frequency fSCK 0 25 MHz VDD = 2.0 V to 2.7 V 15
SCK clock frequency fSCK 0 40 MHz VDD = 2.7 V to 3.6 V 15
Clock HIGH time tCH 20 ns VDD = 2.0 V to 2.7 V 15
Clock HIGH time tCH 11 ns VDD = 2.7 V to 3.6 V 15
Clock LOW time tCL 20 ns VDD = 2.0 V to 2.7 V 15
Clock LOW time tCL 11 ns VDD = 2.7 V to 3.6 V 15
Chip select setup tCSU 12 ns VDD = 2.0 V to 2.7 V 15
Chip select setup tCSU 10 ns VDD = 2.7 V to 3.6 V 15
Chip select hold tCSH 12 ns VDD = 2.0 V to 2.7 V 15
Chip select hold tCSH 10 ns VDD = 2.7 V to 3.6 V 15
Output disable time tOD 20 ns VDD = 2.0 V to 2.7 V 15
Output disable time tOD 12 ns VDD = 2.7 V to 3.6 V 15
Output data valid time tODV 18 ns VDD = 2.0 V to 2.7 V 15
Output data valid time tODV 9 ns VDD = 2.7 V to 3.6 V 15
Data in rise time tR 50 ns VDD = 2.0 V to 2.7 V 15
Data in fall time tF 50 ns VDD = 2.0 V to 2.7 V 15
Data setup time tSU 8 ns VDD = 2.0 V to 2.7 V 15
Data setup time tSU 5 ns VDD = 2.7 V to 3.6 V 15
Data hold time tH 8 ns VDD = 2.0 V to 2.7 V 15
Data hold time tH 5 ns VDD = 2.7 V to 3.6 V 15
HOLD setup time tHS 12 ns VDD = 2.0 V to 2.7 V 15
HOLD setup time tHS 10 ns VDD = 2.7 V to 3.6 V 15
HOLD LOW to HI-Z tHZ 25 ns VDD = 2.0 V to 2.7 V 15
HOLD LOW to HI-Z tHZ 20 ns VDD = 2.7 V to 3.6 V 15
HOLD HIGH to data active tLZ 25 ns VDD = 2.0 V to 2.7 V 15
HOLD HIGH to data active tLZ 20 ns VDD = 2.7 V to 3.6 V 15
Power-up VDD(min) to first access (CS LOW) tPU 250 µs VDD(min) to first access 17
VDD power-up ramp rate tVR 50 µs/V 17
VDD power-down ramp rate tVF 100 µs/V 17
Recovery time from sleep mode tREC 400 µs 17

CAD (KiCad official)

  • Symbol: FM25V05-GTR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: fm25v05-gtr-etched.step / fm25v05-gtr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); fm25v05-gtr.step / fm25v05-gtr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Cypress Semicon datasheet (22 pp, sha256 d1dce7dcdcc9a6f2, retrieved 2026-10-21, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF