component
FM25CL64B-GTR
Public Made by Adomby adom
Infineon FRAM, SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
main
Ray
fm25cl64b-gtr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC bo…
066e90e
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217
{
"schema_version": 1,
"type": "component",
"slug": "fm25cl64b-gtr",
"title": "FM25CL64B-GTR",
"brief": "Infineon FRAM, SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
"version": "0.2.0",
"license": "CC-BY-SA-4.0",
"tags": [
"component",
"memory",
"fm25cl64b-gtr"
],
"component": {
"mpn": "FM25CL64B-GTR",
"manufacturer": "Infineon",
"package": "SOIC-8",
"pin_count": 8,
"category": "Memory",
"subcategory": "FRAM",
"datasheet": "https://datasheet.lcsc.com/datasheet/pdf/dc6c1cf04e7c4f23ac673c6696435ee2.pdf",
"parts": {
"symbol": "fm25cl64b-gtr.kicad_sym",
"footprint": "fm25cl64b-gtr.kicad_mod",
"model_3d": "fm25cl64b-gtr-etched.glb",
"model_3d_plain": "fm25cl64b-gtr.glb",
"model_3d_step": "fm25cl64b-gtr-etched.step",
"model_3d_step_plain": "fm25cl64b-gtr.step",
"lbr": "fm25cl64b-gtr.lbr"
},
"distributor_links": {},
"pins": [
{
"number": "1",
"name": "CS",
"type": "input",
"description": "Chip Select (active LOW). When HIGH, the device enters low-power standby mode, ignores other inputs, and tri-states the output. A falling edge on CS internally activates the SCK signal and must occur before every opcode."
},
{
"number": "2",
"name": "SO",
"type": "output",
"description": "Serial Output (MISO). Driven during a read and tri-stated at all other times, including when HOLD is LOW. Data transitions on the falling edge of SCK."
},
{
"number": "3",
"name": "WP",
"type": "input",
"description": "Write Protect (active LOW). Prevents write operations to the Status Register when WPEN=1. Must be tied to VDD if not used."
},
{
"number": "4",
"name": "VSS",
"type": "power_in",
"description": "Ground reference for the device. Must be connected to system ground."
},
{
"number": "5",
"name": "SI",
"type": "input",
"description": "Serial Input (MOSI). All data is input on this pin, sampled on the rising edge of SCK. Should always be driven to a valid logic level to meet IDD specs. May be tied to SO for a single-pin data interface."
},
{
"number": "6",
"name": "SCK",
"type": "input",
"description": "Serial Clock. All I/O activity is synchronized to this clock. Inputs are latched on the rising edge and outputs occur on the falling edge. Clock frequency 0 to 20 MHz; may be interrupted at any time."
},
{
"number": "7",
"name": "HOLD",
"type": "input",
"description": "HOLD (active LOW). When LOW, suspends the current SPI operation; device ignores transitions on SCK and CS. Transitions must occur while SCK is LOW. Must be tied to VDD if not used."
},
{
"number": "8",
"name": "VDD",
"type": "power_in",
"description": "Power supply input to the device. Operating range 2.7 V to 3.65 V."
}
],
"provenance": {
"extractor": "ds2sf",
"datasheet": {
"url": "https://datasheet.lcsc.com/datasheet/pdf/dc6c1cf04e7c4f23ac673c6696435ee2.pdf",
"pages": 21,
"sha256": "7c6df2f70b3e907d",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 8,
"described": 8,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"pin1": {
"pad": "1",
"at": [
-2.475,
-1.905
],
"corner": "top-left",
"source": "silk-marker",
"derived_from": "SOIC-8_3.9x4.9mm_P1.27mm@sha256:074ecb2092b24fa4",
"mark": "drawn"
},
"models_3d": [
{
"file": "fm25cl64b-gtr.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6,
4.9,
1.75
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
"checked": "2026-10-07",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "fm25cl64b-gtr-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6,
4.9,
1.75
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "a78a20bf61db45986c9e16b1e61e4c90eb77c5115631860679bfb68c4f585bf3",
"checked": "2026-11-03",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
},
"metadata": {
"specs": {
"Manufacturer": "Infineon",
"Package": "SOIC-8",
"Category": "Memory",
"Pins": "8"
}
},
"sections": [
"hero",
"viewers",
"readme",
"breadcrumbs",
"info"
],
"discovery_triggers": [
"fm25cl64b-gtr"
],
"discovery_pitch": "FM25CL64B-GTR (Infineon) component page with datasheet-verified CAD.",
"author": {
"name": "Ray"
},
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"fm25cl64b-gtr.kicad_sym",
"fm25cl64b-gtr.kicad_mod",
"fm25cl64b-gtr.glb",
"fm25cl64b-gtr.step",
"fm25cl64b-gtr-etched.step",
"fm25cl64b-gtr.lbr",
"docs/hero.png",
"docs/fm25cl64b-gtr-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html"
],
"visibility": {
"public": true
},
"variants": [
{
"mpn": "FM25CL64B-GTRG",
"kind": "packaging"
},
{
"mpn": "FM25CL64B-GTR",
"kind": "packaging"
},
{
"mpn": "FM25CL64B-GTRDG",
"kind": "packaging"
},
{
"mpn": "FM25CL64B-GTRDGTR",
"kind": "packaging"
}
],
"updated_at": "2026-09-24T20:40:41.838Z"
}