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FDS8962C-NL-VB
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VBsemi Elec MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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FDS8962C-NL-VB
VBsemi Elec · MOSFETs · SO-8
FDS8962C-NL-VB from VBsemi Elec, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of the first MOSFET (S1) of the dual N- and P-channel 30 V pair. |
| 2 | G1 | input | Gate of the first MOSFET (G1), rated for VGS of ±20 V. |
| 3 | S2 | passive | Source of the second MOSFET (S2) of the dual N- and P-channel 30 V pair. |
| 4 | G2 | input | Gate of the second MOSFET (G2), rated for VGS of ±20 V. |
| 5 | D2 | passive | Drain of the second MOSFET (D2), shorted internally with pin 6. |
| 6 | D2 | passive | Drain of the second MOSFET (D2), shorted internally with pin 5. |
| 7 | D1 | passive | Drain of the first MOSFET (D1), shorted internally with pin 8. |
| 8 | D1 | passive | Drain of the first MOSFET (D1), shorted internally with pin 7. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | VBsemi Elec |
| Package | SO-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage (N-Ch) | VDS | 30 | V | TA = 25 °C | 1 | ||
| Drain-Source Voltage (P-Ch) | VDS | -30 | V | TA = 25 °C | 1 | ||
| Gate-Source Voltage | VGS | -20 | 20 | V | N-Ch and P-Ch | 1 | |
| Continuous Drain Current (N-Ch) | ID | 8 | A | TC = 25 °C, TJ = 150 °C, package limited | 1 | ||
| Continuous Drain Current (P-Ch) | ID | -8 | A | TC = 25 °C, TJ = 150 °C, package limited | 1 | ||
| Pulsed Drain Current | IDM | 40 | A | 10 µs pulse width, N-Ch (P-Ch -40) | 1 | ||
| Single Pulse Avalanche Current (N-Ch) | IAS | 10 | A | L = 0.1 mH | 1 | ||
| Single Pulse Avalanche Current (P-Ch) | IAS | 20 | A | L = 0.1 mH | 1 | ||
| Maximum Power Dissipation | PD | 2 | W | TA = 25 °C, both channels, note b, c | 1 | ||
| Operating Junction and Storage Temperature Range | TJ, Tstg | -55 | 150 | °C | 1 | ||
| Junction-to-Ambient (N-Ch) | RthJA | 50 | 62.5 | °C/W | t ≤ 10 s, N-Channel | 1 | |
| Junction-to-Ambient (P-Ch) | RthJA | 47 | 62.5 | °C/W | t ≤ 10 s, P-Channel | 1 | |
| Junction-to-Foot (N-Ch) | RthJF | 30 | 40 | °C/W | Steady state, N-Channel | 1 | |
| Junction-to-Foot (P-Ch) | RthJF | 29 | 38 | °C/W | Steady state, P-Channel | 1 | |
| Drain-Source Breakdown Voltage (P-Ch) | VDS | -30 | V | VGS = 0 V, ID = - 250 µA | 2 | ||
| Gate Threshold Voltage (P-Ch) | VGS(th) | -2 | -1 | V | VDS = VGS, ID = - 250 µA | 2 | |
| Gate-Body Leakage (N-Ch) | IGSS | -100 | 100 | nA | VDS = 0 V, VGS = ± 12 V | 2 | |
| Gate-Body Leakage (P-Ch) | IGSS | -100 | 100 | nA | VDS = 0 V, VGS = ± 12 V | 2 | |
| Zero Gate Voltage Drain Current (N-Ch) | IDSS | 1 | µA | VDS = 30 V, VGS = 0 V | 2 | ||
| Zero Gate Voltage Drain Current (P-Ch) | IDSS | -1 | µA | VDS = - 30 V, VGS = 0 V | 2 | ||
| Zero Gate Voltage Drain Current (N-Ch) | IDSS | 10 | µA | VDS = 30 V, VGS = 0 V, TJ = 55 °C | 2 | ||
| Zero Gate Voltage Drain Current (P-Ch) | IDSS | -10 | µA | VDS = - 30 V, VGS = 0 V, TJ = 55 °C | 2 | ||
| On-State Drain Current (N-Ch) | ID(on) | 20 | A | VDS = 5 V, VGS = 10 V | 2 | ||
| On-State Drain Current (P-Ch) | ID(on) | -20 | A | VDS = - 5 V, VGS = - 10 V | 2 | ||
| Drain-Source On-State Resistance (N-Ch) | RDS(on) | 0.024 | Ω | VGS = 4.5 V, ID = 6.6 A | 2 | ||
| Drain-Source On-State Resistance (P-Ch) | RDS(on) | 0.04 | Ω | VGS = - 10 V, ID = - 8 A | 2 | ||
| Drain-Source On-State Resistance (P-Ch) | RDS(on) | 0.05 | Ω | VGS = - 4.5 V, ID = - 5 A | 2 | ||
| Gate Resistance (N-Ch) | Rg | 0.3 | 1 | 2.3 | Ω | f = 1 MHz | 2 |
| Gate Resistance (P-Ch) | Rg | 1.2 | 5.7 | 9.6 | Ω | f = 1 MHz | 2 |
| Turn-On Delay Time (N-Ch) | td(on) | 4 | 8 | ns | VDD = 20 V, RL = 3.7 Ω, ID ≅ 5.4 A, VGEN = 10 V, Rg = 1 Ω | 3 | |
| Turn-On Delay Time (P-Ch) | td(on) | 10 | 16 | ns | VDD = - 20 V, RL = 2 Ω, ID ≅ - 10 A, VGEN = - 10 V, Rg = 1 Ω | 3 | |
| Body Diode Voltage (N-Ch) | VSD | 0.81 | 1.2 | V | IS = 5.4 A | 3 | |
| Body Diode Voltage (P-Ch) | VSD | -0.77 | -1.2 | V | IS = - 2 A | 3 | |
| Forward Transconductance (N-Ch) | gfs | 27 | S | VDS = 15 V, ID = 6.8 A | 2 | ||
| Forward Transconductance (P-Ch) | gfs | 25 | S | VDS = - 15 V, ID = - 6.7 A | 2 |
CAD (KiCad official)
- Symbol:
FDS8962C-NL-VB - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
fds8962c-nl-vb-etched.step/fds8962c-nl-vb-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);fds8962c-nl-vb.step/fds8962c-nl-vb.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: VBsemi Elec datasheet (14 pp, sha256
4f36c3b0c62ffe45, retrieved 2026-10-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# FDS8962C-NL-VB
**VBsemi Elec** · MOSFETs · SO-8
FDS8962C-NL-VB from VBsemi Elec, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of the first MOSFET (S1) of the dual N- and P-channel 30 V pair. |
| 2 | G1 | input | Gate of the first MOSFET (G1), rated for VGS of ±20 V. |
| 3 | S2 | passive | Source of the second MOSFET (S2) of the dual N- and P-channel 30 V pair. |
| 4 | G2 | input | Gate of the second MOSFET (G2), rated for VGS of ±20 V. |
| 5 | D2 | passive | Drain of the second MOSFET (D2), shorted internally with pin 6. |
| 6 | D2 | passive | Drain of the second MOSFET (D2), shorted internally with pin 5. |
| 7 | D1 | passive | Drain of the first MOSFET (D1), shorted internally with pin 8. |
| 8 | D1 | passive | Drain of the first MOSFET (D1), shorted internally with pin 7. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | VBsemi Elec |
| Package | SO-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage (N-Ch) | VDS | | | 30 | V | TA = 25 °C | 1 |
| Drain-Source Voltage (P-Ch) | VDS | | | -30 | V | TA = 25 °C | 1 |
| Gate-Source Voltage | VGS | -20 | | 20 | V | N-Ch and P-Ch | 1 |
| Continuous Drain Current (N-Ch) | ID | | | 8 | A | TC = 25 °C, TJ = 150 °C, package limited | 1 |
| Continuous Drain Current (P-Ch) | ID | | | -8 | A | TC = 25 °C, TJ = 150 °C, package limited | 1 |
| Pulsed Drain Current | IDM | | | 40 | A | 10 µs pulse width, N-Ch (P-Ch -40) | 1 |
| Single Pulse Avalanche Current (N-Ch) | IAS | | | 10 | A | L = 0.1 mH | 1 |
| Single Pulse Avalanche Current (P-Ch) | IAS | | | 20 | A | L = 0.1 mH | 1 |
| Maximum Power Dissipation | PD | | | 2 | W | TA = 25 °C, both channels, note b, c | 1 |
| Operating Junction and Storage Temperature Range | TJ, Tstg | -55 | | 150 | °C | | 1 |
| Junction-to-Ambient (N-Ch) | RthJA | | 50 | 62.5 | °C/W | t ≤ 10 s, N-Channel | 1 |
| Junction-to-Ambient (P-Ch) | RthJA | | 47 | 62.5 | °C/W | t ≤ 10 s, P-Channel | 1 |
| Junction-to-Foot (N-Ch) | RthJF | | 30 | 40 | °C/W | Steady state, N-Channel | 1 |
| Junction-to-Foot (P-Ch) | RthJF | | 29 | 38 | °C/W | Steady state, P-Channel | 1 |
| Drain-Source Breakdown Voltage (P-Ch) | VDS | -30 | | | V | VGS = 0 V, ID = - 250 µA | 2 |
| Gate Threshold Voltage (P-Ch) | VGS(th) | -2 | | -1 | V | VDS = VGS, ID = - 250 µA | 2 |
| Gate-Body Leakage (N-Ch) | IGSS | -100 | | 100 | nA | VDS = 0 V, VGS = ± 12 V | 2 |
| Gate-Body Leakage (P-Ch) | IGSS | -100 | | 100 | nA | VDS = 0 V, VGS = ± 12 V | 2 |
| Zero Gate Voltage Drain Current (N-Ch) | IDSS | | | 1 | µA | VDS = 30 V, VGS = 0 V | 2 |
| Zero Gate Voltage Drain Current (P-Ch) | IDSS | | | -1 | µA | VDS = - 30 V, VGS = 0 V | 2 |
| Zero Gate Voltage Drain Current (N-Ch) | IDSS | | | 10 | µA | VDS = 30 V, VGS = 0 V, TJ = 55 °C | 2 |
| Zero Gate Voltage Drain Current (P-Ch) | IDSS | | | -10 | µA | VDS = - 30 V, VGS = 0 V, TJ = 55 °C | 2 |
| On-State Drain Current (N-Ch) | ID(on) | 20 | | | A | VDS = 5 V, VGS = 10 V | 2 |
| On-State Drain Current (P-Ch) | ID(on) | -20 | | | A | VDS = - 5 V, VGS = - 10 V | 2 |
| Drain-Source On-State Resistance (N-Ch) | RDS(on) | | 0.024 | | Ω | VGS = 4.5 V, ID = 6.6 A | 2 |
| Drain-Source On-State Resistance (P-Ch) | RDS(on) | | 0.04 | | Ω | VGS = - 10 V, ID = - 8 A | 2 |
| Drain-Source On-State Resistance (P-Ch) | RDS(on) | | 0.05 | | Ω | VGS = - 4.5 V, ID = - 5 A | 2 |
| Gate Resistance (N-Ch) | Rg | 0.3 | 1 | 2.3 | Ω | f = 1 MHz | 2 |
| Gate Resistance (P-Ch) | Rg | 1.2 | 5.7 | 9.6 | Ω | f = 1 MHz | 2 |
| Turn-On Delay Time (N-Ch) | td(on) | | 4 | 8 | ns | VDD = 20 V, RL = 3.7 Ω, ID ≅ 5.4 A, VGEN = 10 V, Rg = 1 Ω | 3 |
| Turn-On Delay Time (P-Ch) | td(on) | | 10 | 16 | ns | VDD = - 20 V, RL = 2 Ω, ID ≅ - 10 A, VGEN = - 10 V, Rg = 1 Ω | 3 |
| Body Diode Voltage (N-Ch) | VSD | | 0.81 | 1.2 | V | IS = 5.4 A | 3 |
| Body Diode Voltage (P-Ch) | VSD | | -0.77 | -1.2 | V | IS = - 2 A | 3 |
| Forward Transconductance (N-Ch) | gfs | | 27 | | S | VDS = 15 V, ID = 6.8 A | 2 |
| Forward Transconductance (P-Ch) | gfs | | 25 | | S | VDS = - 15 V, ID = - 6.7 A | 2 |
## CAD (KiCad official)
- Symbol: `FDS8962C-NL-VB`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files: `fds8962c-nl-vb-etched.step` / `fds8962c-nl-vb-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `fds8962c-nl-vb.step` / `fds8962c-nl-vb.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [VBsemi Elec datasheet](docs/fds8962c-nl-vb-datasheet.pdf) (14 pp, sha256 `4f36c3b0c62ffe45`, retrieved 2026-10-27, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/fds8962c-nl-vb-datasheet.pdf)