component
FDS8878
Public Made by Adomby adom
UMW MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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FDS8878
UMW · MOSFETs · SOP-8
FDS8878 from UMW, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | SOURCE terminal of the N-channel MOSFET, one of three source pins (1, 2, 3) that are internally common. |
| 2 | S | passive | SOURCE terminal of the N-channel MOSFET, one of three source pins (1, 2, 3) that are internally common. |
| 3 | S | passive | SOURCE terminal of the N-channel MOSFET, one of three source pins (1, 2, 3) that are internally common. |
| 4 | G | input | GATE terminal of the N-channel MOSFET, which controls the channel; the datasheet gives no pin-specific voltage limit for this pin (VGS absolute maximum is ±20 V). |
| 5 | D | passive | DRAIN terminal of the N-channel MOSFET, one of four drain pins (5, 6, 7, 8) that are internally common. |
| 6 | D | passive | DRAIN terminal of the N-channel MOSFET, one of four drain pins (5, 6, 7, 8) that are internally common. |
| 7 | D | passive | DRAIN terminal of the N-channel MOSFET, one of four drain pins (5, 6, 7, 8) that are internally common. |
| 8 | D | passive | DRAIN terminal of the N-channel MOSFET, one of four drain pins (5, 6, 7, 8) that are internally common. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | UMW |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | BVDSS | 30 | V | ID=250µA, VGS=0V | 3 | ||
| Zero Gate Voltage Drain Current | IDSS | 1 | µA | VDS=24V, VGS=0V | 3 | ||
| Zero Gate Voltage Drain Current (TJ=150°C) | IDSS | 250 | µA | VDS=24V, VGS=0V, TJ=150°C | 3 | ||
| Gate to Source Leakage Current | IGSS | -100 | 100 | nA | VGS=±20V | 3 | |
| Gate to Source Threshold Voltage | VGS(th) | 1.2 | 2.5 | V | VDS=VGS, ID=250μA | 3 | |
| Drain to Source On Resistance (VGS=10V) | RDS(ON) | 14 | mΩ | ID=10.2A, VGS=10V | 3 | ||
| Drain to Source On Resistance (VGS=4.5V) | RDS(ON) | 17 | mΩ | ID=9.3A, VGS=4.5V | 3 | ||
| Drain to Source On Resistance (TC=150°C) | RDS(ON) | 22.7 | mΩ | ID=10.2A, VGS=10V, TC=150°C | 3 | ||
| Source to Drain Diode Voltage | VSD | 1.25 | V | ISD=10.2A | 4 | ||
| Source to Drain Diode Voltage | VSD | 1 | V | ISD=2.1A | 4 | ||
| Drain-Source Voltage | VDSS | 30 | V | TA=25°C unless otherwise noted | 1 | ||
| Gate-Source Voltage | VGS | -20 | 20 | V | TA=25°C unless otherwise noted | 1 | |
| Drain Current Continuous | ID | 10.2 | A | TA=25°C, VGS=10V, RθJA=50°C/W | 1 | ||
| Drain Current Continuous | ID | 9.3 | A | TA=25°C, VGS=4.5V, RθJA=50°C/W | 1 | ||
| Drain Current Pulsed | 80 | A | 1 | ||||
| Single Pulse Avalanche Energy | EAS | 57 | mJ | Starting TJ=25°C, L=1mH, IAS=10.7A, VDD=30V, VGS=10V (Note 1) | 1 | ||
| Power Dissipation | PD | 2.5 | W | TA=25°C unless otherwise noted | 1 | ||
| Power Dissipation Derating | 20 | mW/°C | Derate above 25°C | 1 | |||
| Operating and Storage Temperature | TJ,TSTG | -55 | 150 | °C | 1 | ||
| Thermal Resistance, Junction to Case | RθJC | 25 | °C/W | Note 2 | 2 | ||
| Thermal Resistance, Junction to Ambient | RθJA | 50 | °C/W | Note 2a: mounted on 1 in² pad of 2 oz copper | 2 | ||
| Thermal Resistance, Junction to Ambient | RθJA | 125 | °C/W | Note 2b: mounted on minimum pad | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθJA is determined by the user’s board design. a) 50°C/W when mounted on a 1in 2 pad of 2 oz copper. | 4 |
CAD (KiCad official)
- Symbol:
FDS8878 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
fds8878-etched.step/fds8878-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);fds8878.step/fds8878.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: UMW datasheet (11 pp, sha256
2cd438c7d2ba36b2, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).