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Ray Publish 0.1.0 fca2f8a 20d ago

FDS6912A-TP

TECH PUBLIC · MOSFETs · SOP-8

FDS6912A-TP from TECH PUBLIC, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source of N-channel MOSFET 1; VDS rated 30 V.
2 G1 input Gate of N-channel MOSFET 1; VGS maximum ±20 V, threshold 1 V min to 3 V max.
3 S2 passive Source of N-channel MOSFET 2; VDS rated 30 V.
4 G2 input Gate of N-channel MOSFET 2; VGS maximum ±20 V, threshold 1 V min to 3 V max.
5 D2 passive Drain of N-channel MOSFET 2; continuous drain current 7 A at TA=25°C, pulsed 24 A.
6 D2 passive Drain of N-channel MOSFET 2; continuous drain current 7 A at TA=25°C, pulsed 24 A.
7 D1 passive Drain of N-channel MOSFET 1; continuous drain current 7 A at TA=25°C, pulsed 24 A.
8 D1 passive Drain of N-channel MOSFET 1; continuous drain current 7 A at TA=25°C, pulsed 24 A.

Key specifications

Parameter Value
Manufacturer TECH PUBLIC
Package SOP-8
Category Transistors/Thyristors
Pins 8

CAD (KiCad official)

  • Symbol: FDS6912A-TP
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: fds6912a-tp-etched.step / fds6912a-tp-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); fds6912a-tp.step / fds6912a-tp.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TECH PUBLIC datasheet (5 pp, sha256 2c4f0273edeb923c, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF