component
FDS6912A
Public Made by Adomby adom
UMW MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownFDS6912A
UMW · MOSFETs · SOP-8
FDS6912A from UMW, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S2 | passive | Source of MOSFET 2 (channel 2 of the dual 30V N-channel device). |
| 2 | G2 | input | Gate of MOSFET 2, rated for VGS of ±20V maximum. |
| 3 | S1 | passive | Source of MOSFET 1 (channel 1 of the dual 30V N-channel device). |
| 4 | G1 | input | Gate of MOSFET 1, rated for VGS of ±20V maximum. |
| 5 | D2 | passive | Drain of MOSFET 2, tied with pin 6, rated 30V VDSS. |
| 6 | D2 | passive | Drain of MOSFET 2, tied with pin 5, rated 30V VDSS. |
| 7 | D1 | passive | Drain of MOSFET 1, tied with pin 8, rated 30V VDSS. |
| 8 | D1 | passive | Drain of MOSFET 1, tied with pin 7, rated 30V VDSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | UMW |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDSS | 30 | V | TA=25°C | 1 | ||
| Gate-Source Voltage | VGSS | -20 | 20 | V | TA=25°C | 1 | |
| Drain Current, Continuous | ID | 6 | A | 1 | |||
| Drain Current, Pulsed | 20 | A | 1 | ||||
| Power Dissipation for Single Operation | PD | 1.6 | W | Note 1a | 1 | ||
| Power Dissipation for Single Operation | PD | 1 | W | Note 1b | 1 | ||
| Power Dissipation for Single Operation | PD | 0.9 | W | Note 1c | 1 | ||
| Operating and Storage Junction Temperature Range | TJ, TSTG | -55 | 150 | °C | 1 | ||
| Thermal Resistance, Junction-to-Ambient | RθJA | 78 | °C/W | Note 1a | 2 | ||
| Thermal Resistance, Junction-to-Case | RθJC | 40 | °C/W | Note 1 | 2 | ||
| Drain-Source Breakdown Voltage | BVDSS | 30 | V | ID=250µA, VGS=0V | 3 | ||
| Zero Gate Voltage Drain Current | IDSS | 1 | µA | VDS=24V, VGS=0V | 3 | ||
| Zero Gate Voltage Drain Current (TJ=55°C) | IDSS | 10 | µA | VDS=24V, VGS=0V, TJ=55°C | 3 | ||
| Gate-Body Leakage | IGSS | -100 | 100 | nA | VGS=±20V, VDS=0V | 3 | |
| Gate Threshold Voltage | VGS(th) | 1 | 1.9 | 3 | V | VDS=VGS, ID=250µA | 3 |
| Static Drain-Source On-Resistance | RDS(ON) | 19 | 28 | mΩ | VGS=10V, ID=6A | 3 | |
| Static Drain-Source On-Resistance | RDS(ON) | 24 | 35 | mΩ | VGS=4.5V, ID=5A | 3 | |
| Maximum Continuous Drain-Source Diode Forward Current | IS | 1.3 | A | 3 | |||
| Drain-Source Diode Forward Voltage | VSD | 0.75 | 1.2 | V | VGS=0V, IS=1.3A (Note 2) | 4 |
CAD (KiCad official)
- Symbol:
FDS6912A - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
fds6912a-etched.step/fds6912a-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);fds6912a.step/fds6912a.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: UMW datasheet (9 pp, sha256
5f266072cf099050, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).