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FDS6612A

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UMW MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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FDS6612A

UMW · MOSFETs · SOP-8

FDS6612A from UMW, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S passive Source terminal of the N-channel MOSFET (pins 1, 2 and 3 are tied together as SOURCE); device VDSS is 30 V and VGSS is ±20 V.
2 S passive Source terminal of the N-channel MOSFET (pins 1, 2 and 3 are tied together as SOURCE); device VDSS is 30 V and VGSS is ±20 V.
3 S passive Source terminal of the N-channel MOSFET (pins 1, 2 and 3 are tied together as SOURCE); device VDSS is 30 V and VGSS is ±20 V.
4 G input Gate terminal; gate-source voltage is rated at ±20 V maximum (VGSS), with VGS(th) typically 1.9 V.
5 D passive Drain terminal (pins 5, 6, 7 and 8 are tied together as DRAIN); continuous drain current is rated at 8.4 A.
6 D passive Drain terminal (pins 5, 6, 7 and 8 are tied together as DRAIN); continuous drain current is rated at 8.4 A.
7 D passive Drain terminal (pins 5, 6, 7 and 8 are tied together as DRAIN); continuous drain current is rated at 8.4 A.
8 D passive Drain terminal (pins 5, 6, 7 and 8 are tied together as DRAIN); continuous drain current is rated at 8.4 A.

Key specifications

Parameter Value
Manufacturer UMW
Package SOP-8
Category Transistors/Thyristors
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Voltage VDSS 30 V 1
Gate-Source Voltage VGSS -20 20 V 1
Drain Current, Continuous ID 8.4 A Note 1a 1
Drain Current, Pulsed ID 40 A Note 1a 1
Single Pulse Avalanche Energy EAS 24 mJ Note 3: TJ=25°C, L=1mH, IA=7A, VDD=27V, VGS=10V 1
Power Dissipation for Single Operation PD 2.5 W Note 1a 1
Power Dissipation for Single Operation PD 1 W Note 1b 1
Operating and Storage Junction Temperature Range TJ, TSTG -55 150 °C 1
Thermal Resistance, Junction-to-Ambient RθJA 50 °C/W Note 1a: mounted on 1 in² pad of 2 oz copper 2
Thermal Resistance, Junction-to-Ambient RθJA 125 °C/W Note 1b: mounted on minimum pad 2
Thermal Resistance, Junction-to-Case RθJC 25 °C/W Note 1 2
Drain-Source Breakdown Voltage BVDSS 30 V ID=250µA, VGS=0V 3
Zero Gate Voltage Drain Current IDSS 1 µA VDS=24V, VGS=0V 3
Zero Gate Voltage Drain Current (TJ=55°C) IDSS 100 µA VDS=24V, VGS=0V, TJ=55°C 3
Gate-Body Leakage, Forward/Reverse IGSS -100 100 nA VGS=±20V, VDS=0V 3
Gate Threshold Voltage VGS(th) 1 1.9 3 V VDS=VGS, ID=250µA 3
On-State Drain Current ID(ON) 20 A VGS=10V, VDS=5V 3
Static Drain-Source On-Resistance RDS(ON) 19 22 mΩ VGS=10V, ID=8.4A 3
Static Drain-Source On-Resistance RDS(ON) 24 30 mΩ VGS=4.5V, ID=7.2A 3
Maximum Continuous Drain-Source Diode Forward Current IS 2.1 A 4
Drain-Source Diode Forward Voltage VSD 0.77 1.2 V VGS=0V, IS=2.1A (Note 2) 4

CAD (KiCad official)

  • Symbol: FDS6612A
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: fds6612a-etched.step / fds6612a-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); fds6612a.step / fds6612a.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: UMW datasheet (10 pp, sha256 79c9b7b15f2b707d, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF