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FDS4953

TECH PUBLIC · MOSFETs · SOP-8

FDS4953 from TECH PUBLIC, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source of P-channel MOSFET 1; VDSS is -30 V and continuous drain current is -5.3 A at TA=25°C.
2 G1 input Gate of P-channel MOSFET 1; gate-source voltage limit is ±20 V with threshold -1 to -3 V.
3 S2 passive Source of P-channel MOSFET 2; VDSS is -30 V and continuous drain current is -5.3 A at TA=25°C.
4 G2 input Gate of P-channel MOSFET 2; gate-source voltage limit is ±20 V with threshold -1 to -3 V.
5 D2 passive Drain of P-channel MOSFET 2, tied to pin 6; pulsed drain current is -30 A.
6 D2 passive Drain of P-channel MOSFET 2, tied to pin 5; pulsed drain current is -30 A.
7 D1 passive Drain of P-channel MOSFET 1, tied to pin 8; pulsed drain current is -30 A.
8 D1 passive Drain of P-channel MOSFET 1, tied to pin 7; pulsed drain current is -30 A.

Key specifications

Parameter Value
Manufacturer TECH PUBLIC
Package SOP-8
Category Transistors/Thyristors
Pins 8

CAD (KiCad official)

  • Symbol: FDS4953
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: fds4953-etched.step / fds4953-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); fds4953.step / fds4953.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TECH PUBLIC datasheet (5 pp, sha256 fd20d25005ea13a8, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF