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FDS4897C-NL&40V-VB

Public Made by Adom

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VBsemi Elec MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componenttransistors-thyristorsfds4897c-nl&40v-vbfactory-2.0.0extractor-text

Verified FDS4897C-NL&40V-VB

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier lcsc, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: FDS4897C-NL&40V-VB · SO-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 14-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-i7v62rzm/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ fds4897c-nl-40v-vb.kicad_sym✓ fds4897c-nl-40v-vb.kicad_mod✓ fds4897c-nl-40v-vb.step
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

markdown

FDS4897C-NL&40V-VB

VBsemi Elec · MOSFETs · SO-8

FDS4897C-NL&40V-VB from VBsemi Elec, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source of the N-channel MOSFET (Q1), rated for VDS 60 V and ID 5.3 A at TC = 25 °C.
2 G1 input Gate of the N-channel MOSFET (Q1), with a maximum gate-source voltage of ±20 V.
3 S2 passive Source of the P-channel MOSFET (Q2), rated for VDS -60 V and ID -4.9 A at TC = 25 °C.
4 G2 input Gate of the P-channel MOSFET (Q2), with a maximum gate-source voltage of ±20 V.
5 D2 passive Drain of the P-channel MOSFET (Q2), tied internally with pin 6, with a pulsed drain current IDM of -25 A.
6 D2 passive Drain of the P-channel MOSFET (Q2), tied internally with pin 5, with a pulsed drain current IDM of -25 A.
7 D1 passive Drain of the N-channel MOSFET (Q1), tied internally with pin 8, with a pulsed drain current IDM of 20 A.
8 D1 passive Drain of the N-channel MOSFET (Q1), tied internally with pin 7, with a pulsed drain current IDM of 20 A.

Key specifications

Parameter Value
Manufacturer VBsemi Elec
Package SO-8
Category Transistors/Thyristors
Pins 8

CAD (KiCad official)

  • Symbol: FDS4897C-NL&40V-VB
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: fds4897c-nl-40v-vb-etched.step / fds4897c-nl-40v-vb-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); fds4897c-nl-40v-vb.step / fds4897c-nl-40v-vb.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: VBsemi Elec datasheet (14 pp, sha256 d30d40b65b4aae12, retrieved 2026-11-02, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF