component
FDP045N10A
Public Made by Adomby adom
UMW MOSFETs, TO-220. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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FDP045N10A
UMW · MOSFETs · TO-220
FDP045N10A from UMW, in a TO-220. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G | input | GATE terminal of the 100 V N-channel MOSFET; the datasheet gives the gate-to-source voltage limit as VGSS = ±20 V. |
| 2 | D | passive | DRAIN terminal rated for VDSS = 100 V and continuous drain current ID = 164 A at TC = 25°C (silicon limited). |
| 3 | S | passive | SOURCE terminal, the reference for VGS and the return path for drain current; body diode forward voltage VSD is 1.3 V at ISD = 100 A. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | UMW |
| Package | TO-220 |
| Category | Transistors/Thyristors |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain to Source Voltage | VDSS | 100 | V | 1 | |||
| Gate to Source Voltage | VGSS | -20 | 20 | V | 1 | ||
| Drain Current - Continuous | ID | 164 | A | TC=25°C (Silicon Limited) | 1 | ||
| Drain Current - Continuous | ID | 116 | A | TC=100°C (Silicon Limited) | 1 | ||
| Drain Current - Continuous | ID | 120 | A | TC=25°C (packaging limit) | 1 | ||
| Drain Current - Pulsed | IDM | 656 | A | Pulsed | 1 | ||
| Single Pulse Avalanche Energy | EAS | 637 | mJ | 1 | |||
| Diode restores dv/dt peak value | dv/dt | 6 | V/ns | 1 | |||
| Power consumption | PD | 263 | W | TC=25°C | 1 | ||
| Power consumption derating | PD | 1.75 | W/°C | Reduce to above 25°C | 1 | ||
| Maximum Junction-to-Shell Thermal Resistance | RθJC | 0.57 | °C/W | 2 | |||
| Maximum Junction-to-Ambient Thermal Resistance | RθJA | 62.5 | °C/W | 2 | |||
| Storage Temperature Range | TJ, TSTG | -55 | 175 | °C | 2 | ||
| Maximum Lead Temperature for Soldering | TL | 300 | °C | 1/8 inch from case for 5 seconds | 2 | ||
| Drain to Source Breakdown Voltage | BVDSS | 100 | V | ID=250µA, VGS=0V | 3 | ||
| Zero Gate Voltage Drain Current | IDSS | 1 | µA | VDS=80V, VGS=0V | 3 | ||
| Zero Gate Voltage Drain Current | IDSS | 500 | µA | VDS=80V, TJ=150°C | 3 | ||
| Gate-body leakage current | IGSS | -100 | 100 | nA | VGS=±20V, VDS=0V | 3 | |
| Gate threshold voltage | VGS(th) | 2 | 4 | V | VDS=VGS, ID=250µA | 3 | |
| Static on-resistance from drain to source | RDS(ON) | 3.8 | 4.5 | mΩ | VGS=10V, ID=100A | 3 | |
| Input capacitance | Ciss | 3960 | 5270 | pF | VDS=50V, VGS=0V, f=1MHz | 3 | |
| Output capacitance | Coss | 925 | 1230 | pF | VDS=50V, VGS=0V, f=1MHz | 3 | |
| Maximum Pulsed Drain to Source Diode Forward Current (continuous) | IS | 164 | A | 3 | |||
| Maximum Pulsed Drain to Source Diode Forward Current (pulsed) | ISM | 656 | A | 3 | |||
| Drain to Source Diode Forward Voltage | VSD | 1.3 | V | VGS=0V, ISD=100A | 4 |
CAD (KiCad official)
- Symbol:
FDP045N10A - Footprint:
Package_TO_SOT_THT:TO-220-3_Vertical - 3D model: TO-220 (KiCad packages3D, STEP)
- 3D model files:
fdp045n10a-etched.step/fdp045n10a-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);fdp045n10a.step/fdp045n10a.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: UMW datasheet (11 pp, sha256
1da0aa3a310300c3, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# FDP045N10A
**UMW** · MOSFETs · TO-220
FDP045N10A from UMW, in a TO-220. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G | input | GATE terminal of the 100 V N-channel MOSFET; the datasheet gives the gate-to-source voltage limit as VGSS = ±20 V. |
| 2 | D | passive | DRAIN terminal rated for VDSS = 100 V and continuous drain current ID = 164 A at TC = 25°C (silicon limited). |
| 3 | S | passive | SOURCE terminal, the reference for VGS and the return path for drain current; body diode forward voltage VSD is 1.3 V at ISD = 100 A. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | UMW |
| Package | TO-220 |
| Category | Transistors/Thyristors |
| Pins | 3 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain to Source Voltage | VDSS | | | 100 | V | | 1 |
| Gate to Source Voltage | VGSS | -20 | | 20 | V | | 1 |
| Drain Current - Continuous | ID | | | 164 | A | TC=25°C (Silicon Limited) | 1 |
| Drain Current - Continuous | ID | | | 116 | A | TC=100°C (Silicon Limited) | 1 |
| Drain Current - Continuous | ID | | | 120 | A | TC=25°C (packaging limit) | 1 |
| Drain Current - Pulsed | IDM | | | 656 | A | Pulsed | 1 |
| Single Pulse Avalanche Energy | EAS | | | 637 | mJ | | 1 |
| Diode restores dv/dt peak value | dv/dt | | | 6 | V/ns | | 1 |
| Power consumption | PD | | | 263 | W | TC=25°C | 1 |
| Power consumption derating | PD | | | 1.75 | W/°C | Reduce to above 25°C | 1 |
| Maximum Junction-to-Shell Thermal Resistance | RθJC | | | 0.57 | °C/W | | 2 |
| Maximum Junction-to-Ambient Thermal Resistance | RθJA | | | 62.5 | °C/W | | 2 |
| Storage Temperature Range | TJ, TSTG | -55 | | 175 | °C | | 2 |
| Maximum Lead Temperature for Soldering | TL | | | 300 | °C | 1/8 inch from case for 5 seconds | 2 |
| Drain to Source Breakdown Voltage | BVDSS | 100 | | | V | ID=250µA, VGS=0V | 3 |
| Zero Gate Voltage Drain Current | IDSS | | | 1 | µA | VDS=80V, VGS=0V | 3 |
| Zero Gate Voltage Drain Current | IDSS | | | 500 | µA | VDS=80V, TJ=150°C | 3 |
| Gate-body leakage current | IGSS | -100 | | 100 | nA | VGS=±20V, VDS=0V | 3 |
| Gate threshold voltage | VGS(th) | 2 | | 4 | V | VDS=VGS, ID=250µA | 3 |
| Static on-resistance from drain to source | RDS(ON) | | 3.8 | 4.5 | mΩ | VGS=10V, ID=100A | 3 |
| Input capacitance | Ciss | | 3960 | 5270 | pF | VDS=50V, VGS=0V, f=1MHz | 3 |
| Output capacitance | Coss | | 925 | 1230 | pF | VDS=50V, VGS=0V, f=1MHz | 3 |
| Maximum Pulsed Drain to Source Diode Forward Current (continuous) | IS | | | 164 | A | | 3 |
| Maximum Pulsed Drain to Source Diode Forward Current (pulsed) | ISM | | | 656 | A | | 3 |
| Drain to Source Diode Forward Voltage | VSD | | | 1.3 | V | VGS=0V, ISD=100A | 4 |
## CAD (KiCad official)
- Symbol: `FDP045N10A`
- Footprint: `Package_TO_SOT_THT:TO-220-3_Vertical`
- 3D model: TO-220 (KiCad packages3D, STEP)
- 3D model files: `fdp045n10a-etched.step` / `fdp045n10a-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `fdp045n10a.step` / `fdp045n10a.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [UMW datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8763509932354351104) (11 pp, sha256 `1da0aa3a310300c3`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/fdp045n10a-datasheet.pdf)