main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 17d ago
viewers fdd4685: viewers · Ray 17d ago
fdd4685-etched.glb Publish 0.1.0 · Ray 17d ago
fdd4685-etched.step fdd4685: factory component page (tier=lcsc) · Ray 17d ago
fdd4685-hero.glb fdd4685: hero GLB from the etched model (keeps the MPN mark) · Ray 17d ago
fdd4685-hero.overlay.json Publish 0.1.0 · Ray 17d ago
fdd4685.glb Publish 0.1.0 · Ray 17d ago
fdd4685.kicad_mod Publish 0.1.0 · Ray 17d ago
fdd4685.kicad_sym Publish 0.1.0 · Ray 17d ago
fdd4685.lbr Publish 0.1.0 · Ray 17d ago
fdd4685.step Publish 0.1.0 · Ray 17d ago
package.json Publish 0.1.0 · Ray 17d ago
page.json Set visibility: public · Ray 17d ago
README.md Publish 0.1.0 · Ray 17d ago

FDD4685

UMW · MOSFETs · TO-252

FDD4685 from UMW, in a TO-252. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input GATE terminal of the -40 V P-channel MOSFET; gate-to-source voltage is rated at ±20 V (VGS).
2 D passive DRAIN terminal of the -40 V P-channel MOSFET; rated VDS of -40 V with continuous drain current of -32 A (package limited) at TC=25°C.
3 S passive SOURCE terminal of the -40 V P-channel MOSFET; the reference for the ±20 V gate-to-source rating.

Key specifications

Parameter Value
Manufacturer UMW
Package TO-252
Category Transistors/Thyristors
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain to Source Breakdown Voltage BVDSS -40 V ID=-250µA, VGS=0V 3
Zero Gate Voltage Drain Current IDSS -1 µA VDS=-32V, VGS=0V 3
Gate to Source Leakage Current IGSS -100 100 nA VGS=±20V, VDS=0V 3
Gate to Source Threshold Voltage VGS(th) 1 -1.6 -3 V VDS=VGS, ID=-250µA 3
Input Capacitance Ciss 1790 2380 pF VDS=-20V, VGS=0V, f=1MHz 3
Output Capacitance Coss 260 345 pF VDS=-20V, VGS=0V, f=1MHz 3
Reverse Transfer Capacitance Crss 140 205 pF VDS=-20V, VGS=0V, f=1MHz 3
Turn-On Delay Time tD(on) 8 16 ns VDD=-20V, ID=-8.4A, VGS=-10V, RGEN=6Ω 3
Rise Time tr 15 27 ns VDD=-20V, ID=-8.4A, VGS=-10V, RGEN=6Ω 3
Turn-Off Delay Time tD(off) 34 55 ns VDD=-20V, ID=-8.4A, VGS=-10V, RGEN=6Ω 3
Fall Time tf 14 26 ns VDD=-20V, ID=-8.4A, VGS=-10V, RGEN=6Ω 3
Total Gate Charge Qg(TOT) 19 27 nC VDD=-20V, ID=-8.4A, VGS=-5V 3
Source to Drain Diode Forward Voltage VSD -0.85 -1.2 V VGS=0V, IS=-8.4A (Note 2) 3
Reverse Recovery Time trr 30 45 ns IF=-8.4A, di/dt=100A/µs 3
Reverse Recovery Charge Qrr 31 47 nC IF=-8.4A, di/dt=100A/µs 3
Static Drain to Source On Resistance RDS(ON) 23 27 mΩ VGS=-10V, ID=-8.4A 3
Static Drain to Source On Resistance RDS(ON) 30 35 mΩ VGS=-4.5V, ID=-7A 3
Forward Transconductance gFS 23 S VDS=-5V, ID=-8.4A 3
Gate Resistance Rg 4 Ω f=1MHz 3
Gate to Source Gate Charge Qgs 5.6 nC VDD=-20V, ID=-8.4A, VGS=-5V 3
Gate to Drain Miller Charge Qgd 6.1 nC VDD=-20V, ID=-8.4A, VGS=-5V 3
Breakdown Voltage Temperature Coefficient ∆BVDSS/∆TJ -33 mV/°C ID=-250µA, Referenced to 25°C 3
Gate to Source Threshold Voltage Temperature Coefficient ∆VGS(th)/∆TJ 4.9 mV/°C ID=-250µA, Referenced to 25°C 3
Drain to Source Voltage VDS -40 V 1
Gate to Source Voltage VGS -20 20 V 1
Drain Current -Continuous (Package limited) ID -32 A TC=25°C 1
Drain Current -Continuous (Silicon limited) ID -40 A TC=25°C (Note 1) 1
Drain Current -Continuous ID -8.4 A TA=25°C (Note 1a) 1
Drain Current -Pulsed ID -100 A 1
Single Pulse Avalanche Energy EAS 121 mJ (Note 3) 1
Power Dissipation PD 69 W TC=25°C 1
Power Dissipation PD 3 W TA=25°C (Note 1a) 1
Operating and Storage Junction Temperature Range TJ, TSTG -55 150 °C 1
Thermal Resistance, Junction to Case RθJC 1.8 °C/W 2
Thermal Resistance, Junction to Ambient RθJA 40 °C/W Note 1a: 1 in² pad of 2 oz copper 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper solder mounting surface of the drain pins. RθJC is guaranteed by design while RθJA is determined by the user’s board design. a. 40°C/W when mounted on a 1 in 2 pad of 2 oz copper 4

CAD (KiCad official)

  • Symbol: FDD4685
  • Footprint: Package_TO_SOT_SMD:TO-252-2
  • 3D model: TO-252 (KiCad packages3D, STEP)
  • 3D model files: fdd4685-etched.step / fdd4685-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); fdd4685.step / fdd4685.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: UMW datasheet (10 pp, sha256 10a3a0b52c971ae0, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF