component

FDC6330L

Public Made by Adom

by adom

onsemi AC-DC Controllers and Regulators, TSOT-23-6. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Made with kicad-footprint-generator 10.0 · KiCad file format 20260206
Name Last commit message Last updated
docs fdc6330l: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
fdc6330l-etched.fit.json fdc6330l: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
fdc6330l-etched.glb fdc6330l: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
fdc6330l-etched.step fdc6330l: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
fdc6330l.glb Publish 0.1.0 · Ray
fdc6330l.kicad_mod Publish 0.1.0 · Ray
fdc6330l.kicad_sym Publish 0.1.0 · Ray
fdc6330l.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
fdc6330l.step Publish 0.1.0 · Ray
package.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json fdc6330l: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md fdc6330l: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray

FDC6330L

onsemi · AC-DC Controllers and Regulators · TSOT-23-6

FDC6330L from onsemi, in a TSOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 R2 passive Source of internal N-channel control MOSFET Q1. Connected externally to ground through pull-down resistor R2 (typ. 1k-4.7 kΩ) which sets the slew rate of Q2's gate turn-on.
2 VOUT/C1 power_out Drain of internal P-channel power MOSFET Q2; switched output to the load. Tied to pin 3 (both are Q2 drain leads for current handling). Output bypass capacitor C1 (≤1 µF) connects here.
3 VOUT/C1 power_out Drain of internal P-channel power MOSFET Q2; switched output to the load. Tied to pin 2 (both are Q2 drain leads for current handling).
4 VIN/R1 power_in Source of P-channel power MOSFET Q2; connect to the input rail (3-20 V, up to 30 V with proper R1/R2 scaling). External pull-up resistor R1 ties this pin to pin 6 to keep Q2 off when ON/OFF is low.
5 ON/OFF input Gate of internal N-channel control MOSFET Q1. Logic-level enable input with a rated range of 1.5-8 V; drive high to turn the switch on, low to turn it off. Q1 includes Zener ESD protection (>6 kV HBM).
6 R1/C1_GATE passive Drain of control MOSFET Q1 and gate of power MOSFET Q2. External R1 connects this pin back to VIN (pin 4) to pull Q2's gate off; R1/R2 ratio is chosen in the range 10-100. Optional in-rush snub capacitor C1 (≤1000 pF) may be added here for slew-rate control.

Key specifications

Parameter Value
Manufacturer onsemi
Package TSOT-23-6
Category PMIC
Pins 6

Ordering variants

Same part, different packaging or reel option.

  • FDC6330L

CAD (KiCad official)

  • Symbol: FDC6330L
  • Footprint: Package_TO_SOT_SMD:SOT-23-6
  • 3D model: TSOT-23-6 (KiCad packages3D, STEP)
  • 3D model files: fdc6330l-etched.step / fdc6330l-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); fdc6330l.step / fdc6330l.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (6 pp, sha256 044f96d39deffe44, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF