FDC6321C-TP

TECH PUBLIC · MOSFETs · SOT-23-6

FDC6321C-TP from TECH PUBLIC, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	G1	input	Gate of N-channel MOSFET Q1 (VGS ±8 V abs max, threshold 0.45 V min to 1.1 V max).
2	S2	passive	Source of P-channel MOSFET Q2 (VDS -25 V, continuous ID -0.8 A).
3	G2	input	Gate of P-channel MOSFET Q2 (VGS ±8 V abs max, threshold -0.45 V min to -1.3 V max).
4	D2	passive	Drain of P-channel MOSFET Q2 (VDS -25 V, continuous ID -0.8 A, pulsed -1.3 A).
5	S1	passive	Source of N-channel MOSFET Q1 (VDS 25 V, continuous ID 0.8 A).
6	D1	passive	Drain of N-channel MOSFET Q1 (VDS 25 V, continuous ID 0.8 A, pulsed 1.3 A).

Key specifications

Parameter	Value
Manufacturer	TECH PUBLIC
Package	SOT-23-6
Category	Transistors/Thyristors
Pins	6

CAD (KiCad official)

Symbol: FDC6321C-TP
Footprint: Package_TO_SOT_SMD:SOT-23-6
3D model: SOT-23-6 (KiCad packages3D, STEP)
3D model files: fdc6321c-tp-etched.step / fdc6321c-tp-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); fdc6321c-tp.step / fdc6321c-tp.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: TECH PUBLIC datasheet (3 pp, sha256 0cbb9d4a14ae78f8, retrieved 2026-10-17, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# FDC6321C-TP

**TECH PUBLIC** · MOSFETs · SOT-23-6

FDC6321C-TP from TECH PUBLIC, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G1 | input | Gate of N-channel MOSFET Q1 (VGS ±8 V abs max, threshold 0.45 V min to 1.1 V max). |
| 2 | S2 | passive | Source of P-channel MOSFET Q2 (VDS -25 V, continuous ID -0.8 A). |
| 3 | G2 | input | Gate of P-channel MOSFET Q2 (VGS ±8 V abs max, threshold -0.45 V min to -1.3 V max). |
| 4 | D2 | passive | Drain of P-channel MOSFET Q2 (VDS -25 V, continuous ID -0.8 A, pulsed -1.3 A). |
| 5 | S1 | passive | Source of N-channel MOSFET Q1 (VDS 25 V, continuous ID 0.8 A). |
| 6 | D1 | passive | Drain of N-channel MOSFET Q1 (VDS 25 V, continuous ID 0.8 A, pulsed 1.3 A). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | TECH PUBLIC |
| Package | SOT-23-6 |
| Category | Transistors/Thyristors |
| Pins | 6 |

## CAD (KiCad official)

- Symbol: `FDC6321C-TP`
- Footprint: `Package_TO_SOT_SMD:SOT-23-6`
- 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files: `fdc6321c-tp-etched.step` / `fdc6321c-tp-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `fdc6321c-tp.step` / `fdc6321c-tp.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [TECH PUBLIC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590454712936919040) (3 pp, sha256 `0cbb9d4a14ae78f8`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/fdc6321c-tp-datasheet.pdf)