FDC606P

TECH PUBLIC · MOSFETs · SOT-23-6

FDC606P from TECH PUBLIC, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	D	passive	Drain, tied internally with pins 2, 5 and 6; rated VDS -20 V and continuous drain current -7 A (TC = 25°C).
2	D	passive	Drain, tied internally with pins 1, 5 and 6; rated VDS -20 V and continuous drain current -7 A (TC = 25°C).
3	G	input	Gate, with VGS limit of ±12 V and gate threshold voltage of -0.4 V min to -1.1 V max at ID = -250 µA.
4	S	passive	Source of the P-channel MOSFET, with the body diode continuous forward current rated -7 A.
5	D	passive	Drain, tied internally with pins 1, 2 and 6; pulsed drain current -26 A.
6	D	passive	Drain, tied internally with pins 1, 2 and 5; RDS(on) 22 mΩ typ at VGS = -4.5 V.

Key specifications

Parameter	Value
Manufacturer	TECH PUBLIC
Package	SOT-23-6
Category	Transistors/Thyristors
Pins	6

CAD (KiCad official)

Symbol: FDC606P
Footprint: Package_TO_SOT_SMD:SOT-23-6
3D model: SOT-23-6 (KiCad packages3D, STEP)
3D model files: fdc606p-etched.step / fdc606p-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); fdc606p.step / fdc606p.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: TECH PUBLIC datasheet (4 pp, sha256 8a564e1a48b489c2, retrieved 2026-10-18, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# FDC606P

**TECH PUBLIC** · MOSFETs · SOT-23-6

FDC606P from TECH PUBLIC, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | D | passive | Drain, tied internally with pins 2, 5 and 6; rated VDS -20 V and continuous drain current -7 A (TC = 25°C). |
| 2 | D | passive | Drain, tied internally with pins 1, 5 and 6; rated VDS -20 V and continuous drain current -7 A (TC = 25°C). |
| 3 | G | input | Gate, with VGS limit of ±12 V and gate threshold voltage of -0.4 V min to -1.1 V max at ID = -250 µA. |
| 4 | S | passive | Source of the P-channel MOSFET, with the body diode continuous forward current rated -7 A. |
| 5 | D | passive | Drain, tied internally with pins 1, 2 and 6; pulsed drain current -26 A. |
| 6 | D | passive | Drain, tied internally with pins 1, 2 and 5; RDS(on) 22 mΩ typ at VGS = -4.5 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | TECH PUBLIC |
| Package | SOT-23-6 |
| Category | Transistors/Thyristors |
| Pins | 6 |

## CAD (KiCad official)

- Symbol: `FDC606P`
- Footprint: `Package_TO_SOT_SMD:SOT-23-6`
- 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files: `fdc606p-etched.step` / `fdc606p-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `fdc606p.step` / `fdc606p.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [TECH PUBLIC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603115090942586880) (4 pp, sha256 `8a564e1a48b489c2`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/fdc606p-datasheet.pdf)