component

FD6636S

Public Made by Adom

by adom

Fortior Tech Gate Drivers, SOIC-28-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentmotor driver icsfd6636sfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

FD6636S

Fortior Tech · Gate Drivers · SOIC-28-300mil

FD6636S from Fortior Tech, in a SOIC-28-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in Low-side supply voltage, recommended 10 V to 20 V (absolute maximum -0.3 V to 25 V relative to COM), with VCC undervoltage trip at 9.0 V typical.
2 HIN1* input High-side channel 1 input, labeled negative logic (*) in the datasheet; VIH minimum 2.7 V and VIL maximum 0.8 V.
3 HIN2* input High-side channel 2 input, labeled negative logic (*) in the datasheet; VIH minimum 2.7 V and VIL maximum 0.8 V.
4 HIN3* input High-side channel 3 input, labeled negative logic (*) in the datasheet; VIH minimum 2.7 V and VIL maximum 0.8 V.
5 LIN1* input Low-side channel 1 input, labeled negative logic (*) in the datasheet; VIH minimum 2.7 V and VIL maximum 0.8 V.
6 LIN2* input Low-side channel 2 input, labeled negative logic (*) in the datasheet; VIH minimum 2.7 V and VIL maximum 0.8 V.
7 LIN3* input Low-side channel 3 input, labeled negative logic (*) in the datasheet; VIH minimum 2.7 V and VIL maximum 0.8 V.
8 FAULT* output Fault indication output (negative logic) that goes low on overcurrent or low-side undervoltage lockout, with an on-resistance of 50 Ω typical and 75 Ω maximum when asserted.
9 ITRIP input Overcurrent protection input whose detection threshold is 0.46 V typical (0.38 V to 0.54 V) and which shuts off all six outputs when exceeded.
10 EN input Enable input with VIH minimum 2.7 V and VIL maximum 0.8 V; driving it low shuts off all six outputs.
11 RCIN input External RC network pin that sets the fault-clear delay; with R = 2 MΩ and C = 1 nF the reset time is 1.65 ms typical (1.3 ms to 2.0 ms).
12 VSS power_in Logic ground, recommended operating range -5 V to 5 V relative to COM, with absolute maximum VCC -25 V to VCC + 0.3 V.
13 COM power_in Low-side gate driver common and reference point for all voltage ratings in the datasheet.
14 LO3 output Low-side gate drive output for channel 3, swinging between COM and VCC with peak source current 0.21 A typical and peak sink current 0.36 A typical.
15 LO2 output Low-side gate drive output for channel 2, swinging between COM and VCC with peak source current 0.21 A typical and peak sink current 0.36 A typical.
16 LO1 output Low-side gate drive output for channel 1, swinging between COM and VCC with peak source current 0.21 A typical and peak sink current 0.36 A typical.
17 NC unconnected No connection.
18 VS3 power_in High-side floating offset voltage for channel 3, recommended up to 600 V with dVS/dt limited to 50 V/ns.
19 HO3 output High-side gate drive output for channel 3, referenced to VS3 and driven between VS3 and VB3.
20 VB3 power_in High-side floating supply for channel 3, recommended VS3 + 10 V to VS3 + 20 V (absolute maximum -0.3 V to 625 V relative to COM).
21 NC unconnected No connection.
22 VS2 power_in High-side floating offset voltage for channel 2, recommended up to 600 V with dVS/dt limited to 50 V/ns.
23 HO2 output High-side gate drive output for channel 2, referenced to VS2 and driven between VS2 and VB2.
24 VB2 power_in High-side floating supply for channel 2, recommended VS2 + 10 V to VS2 + 20 V (absolute maximum -0.3 V to 625 V relative to COM).
25 NC unconnected No connection.
26 VS1 power_in High-side floating offset voltage for channel 1, recommended up to 600 V with dVS/dt limited to 50 V/ns.
27 HO1 output High-side gate drive output for channel 1, referenced to VS1 and driven between VS1 and VB1.
28 VB1 power_in High-side floating supply for channel 1, recommended VS1 + 10 V to VS1 + 20 V (absolute maximum -0.3 V to 625 V relative to COM).

Key specifications

Parameter Value
Manufacturer Fortior Tech
Package SOIC-28-300mil
Category Motor Driver ICs
Pins 28

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High-side floating absolute voltage VB1,2,3 -0.3 625 V 9
Low-side supply voltage VCC -0.3 25 V 9
Low-side output voltage VLO1,2,3 -0.3 V 9
Offset voltage slew rate range dVS/dt 50 V/ns 9
Power dissipation PD 1.8 W TA ≤ 25C 9
Thermal resistance junction to ambient RthJA 70 ℃/W SOP28 9
Junction temperature range Tj 150 ℃ 9
Storage temperature range Tstg -55 150 ℃ 9
High-side floating offset voltage VS1,2,3 600 V min per note [2] 9
Low-side supply voltage VCC 10 20 V 9
Low-side output voltage VLO1,2,3 0 V 9
Logic ground VSS -5 5 V 9
Ambient temperature TA -40 125 ℃ 10
Floating supply leakage current ILK 0.1 5 μA VB1,2,3 = VS1,2,3 = 600V 10
VBS quiescent current IQBS 90 150 μA VIN = 0V 或 5V 10
VCC quiescent current IQCC 0.9 1.6 μA VIN = 0V 或 5V 10
HIN*/LIN* high-level input threshold voltage VIH 2.7 V 10
HIN*/LIN* low-level input threshold voltage VIL 0.8 V 10
EN high-level input threshold voltage VEN,TH+ 2.7 V 10
EN low-level input threshold voltage VEN,TH- 0.8 V 10
ITRIP overcurrent detection voltage VIT,TH+ 0.38 0.46 0.54 V 10
LIN* high-level input bias current ILIN*+ 70 100 μA VLIN* = 5V 10
LIN* low-level input bias current ILIN*- 110 150 μA VLIN* = 0V 10
HIN* high-level input bias current IHIN*+ 70 100 μA VHIN* = 5V 10
HIN* low-level input bias current IHIN*- 110 150 μA VHIN* = 0V 10
ITRIP high-level input bias current IITRIP+ 300 500 μA VITRIP = 5V 10
ITRIP low-level input bias current IITRIP- 0 1 μA VITRIP = 0V 10
EN high-level input bias current IEN+ 300 500 μA VEN = 5V 11
EN low-level input bias current IEN- 0 1 μA VEN = 0V 11
RCIN input bias current IRCIN 0 1 μA VRCIN = 0V 或 15V 11
VCC undervoltage lockout trip voltage VCCUV+ 8.1 9 9.9 V 11
VCC undervoltage lockout reset voltage VCCUV- 7.5 8.4 9.3 V 11
VCC undervoltage lockout hysteresis voltage VCCUVH 0.4 0.6 V 11
VBS undervoltage lockout trip voltage VBSUV+ 8 8.9 9.8 V 11
VBS undervoltage lockout reset voltage VBSUV- 7.3 8.1 8.9 V 11
VBS undervoltage lockout hysteresis voltage VBSUVH 0.5 0.8 V 11
HO low-level output voltage VOL-H 0.2 0.35 V IO = 20mA 11
LO low-level output voltage VOL-L 0.2 0.35 V IO = 20mA 11
High-level output short-circuit pulsed current IOH 0.14 0.21 A VO = 0V，VIN = 0V，PWD ≤ 10μs 11
Low-level output short-circuit pulsed current IOL 0.24 0.36 A VO = 15V，VIN = 5V，PWD ≤ 10μs 11
RCIN on-resistance RON_RCIN 50 75 Ω 11
FAULT* on-resistance RON_FAULT* 50 75 Ω 11
VS static negative voltage VSN -6.5 -5 V 11
Output rising-edge propagation delay ton 200 300 400 ns CL = 1000pF 11
Output falling-edge propagation delay toff 200 300 400 ns CL = 1000pF 11
Output rise time tr 110 180 ns CL = 1000pF 11
Output fall time tf 45 70 ns CL = 1000pF 11
EN shutdown delay time tEN 200 300 400 ns VEN = 0V 11
ITRIP overcurrent propagation delay tITRIP 275 400 525 ns VITRIP = 5V 11
ITRIP leading-edge blanking time tbl 100 150 ns VIN = 0V, VITRIP = 5V 11
ITRIP to FAULT* propagation delay tFLT 200 325 450 ns VIN = 0V, VITRIP = 5V 11
Input filter time (HIN*, LIN*) tFILIN* 100 200 ns VIN = 0V 11
RCIN reset time tFLTCLR 1.3 1.65 2 ms VIN = 0V, VITRIP = 0V (R = 2M, C = 1nF) 11
Dead time DT 200 300 400 ns VIN = 0V 或 5V 12
High/low-side delay matching MT 40 75 ns 12
Three-channel turn-on and turn-off delay matching MDT 25 70 ns 12
Input and output pulse width matching /pwin-pwout/ 40 75 ns 12
High-side PWM HIN1,2,3* input pulse width 1 μs high-side PWM input (note under table 3-3) 12

CAD (KiCad official)

  • Symbol: FD6636S
  • Footprint: Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm
  • 3D model: SOIC-28-300mil (KiCad packages3D, STEP)
  • 3D model files: fd6636s-etched.step / fd6636s-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); fd6636s.step / fd6636s.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Fortior Tech datasheet (22 pp, sha256 e71c618d7c6feaad, retrieved 2026-10-19, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF