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FCM32F051R8T6

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Flashchip Microelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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FCM32F051R8T6

Flashchip Microelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

FCM32F051R8T6 from Flashchip Microelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup power supply input; the datasheet gives a backup operating voltage of 2.1 to 5.5 V and an absolute maximum of -0.3 to 5.8 V.
2 PC13 bidirectional Standard 5 V TC I/O supplied through the power switch, which sinks only 3 mA, so output use is limited to 2 MHz at 30 pF max and must not source LEDs; additional functions WKUP2, RTC_TAMP1, RTC_TS, RTC_OUT.
3 PC14 bidirectional Standard 5 V TC I/O on the power-switch domain with the same 3 mA and output-use limits as PC13; additional function OSC32_IN (low-speed oscillator input).
4 PC15 bidirectional Standard 5 V TC I/O on the power-switch domain with the same 3 mA and output-use limits as PC13; additional function OSC32_OUT (low-speed oscillator output).
5 PF0 bidirectional 5 V-tolerant FTf I/O with FM+ capability, also the OSC_IN high-speed oscillator input; alternate functions CRS_SYNC and I2C1_SDA.
6 PF1 bidirectional 5 V-tolerant FTf I/O with FM+ capability, also the OSC_OUT high-speed oscillator output; alternate function I2C1_SCL.
7 NRST bidirectional Active-low device reset bidirectional pin with embedded weak pull-up (about 40 kΩ), VIL max 0.3VDD and VIH min 0.445VDD+0.4 V.
8 PC0 bidirectional 5 V-tolerant TTa I/O directly connected to the ADC; alternate function EVENTOUT, additional function ADC_IN10.
9 PC1 bidirectional 5 V-tolerant TTa I/O directly connected to the ADC; alternate function EVENTOUT, additional function ADC_IN11.
10 PC2 bidirectional 5 V-tolerant TTa I/O directly connected to the ADC; alternate functions SPI2_MISO, I2S2_MCK, EVENTOUT, additional function ADC_IN12.
11 PC3 bidirectional 5 V-tolerant TTa I/O directly connected to the ADC; alternate functions SPI2_MOSI, I2S2_SD, EVENTOUT, additional function ADC_IN13.
12 VSSA power_in Analog ground; on this non-48-pin package it is the VSS pin to which the die's VSSA pad is connected.
13 VDDA power_in Analog power supply, 1.8 to 5.5 V, which must always be greater than or equal to VDD and be powered first.
14 PA0 bidirectional 5 V-tolerant TTa I/O directly connected to the ADC; alternate functions USART2_CTS, TIM2_CH1_ETR, COMP1_OUT; additional functions RTC_TAMP2, WKUP1, ADC_IN0, COMP1_INM6.
15 PA1 bidirectional 5 V-tolerant TTa I/O directly connected to the ADC; alternate functions USART2_RTS, TIM2_CH2, TIM15_CH1N, EVENTOUT; additional functions ADC_IN1, COMP1_INP.
16 PA2 bidirectional 5 V-tolerant TTa I/O directly connected to the ADC; alternate functions USART2_TX, TIM2_CH3, TIM15_CH1, COMP2_OUT; additional functions ADC_IN2, WKUP4, COMP2_INM6.
17 PA3 bidirectional 5 V-tolerant TTa I/O directly connected to the ADC; alternate functions USART2_RX, TIM2_CH4, TIM15_CH2; additional functions ADC_IN3, COMP2_INP.
18 VSS power_in Ground reference pin.
19 VDD power_in Digital power supply, 1.8 to 5.5 V, which supplies the I/O and the internal regulator.
20 PA4 bidirectional 5 V-tolerant TTa I/O directly connected to the ADC; alternate functions SPI1_NSS, I2S1_WS, TIM14_CH1, USART2_CK; additional functions COMP1_INM4, COMP2_INM4, ADC_IN4, DAC_OUT1.
21 PA5 bidirectional 5 V-tolerant TTa I/O directly connected to the ADC; alternate functions SPI1_SCK, I2S1_CK, CEC, TIM2_CH1_ETR; additional functions COMP1_INM5, COMP2_INM5, ADC_IN5.
22 PA6 bidirectional 5 V-tolerant TTa I/O directly connected to the ADC; alternate functions SPI1_MISO, I2S1_MCK, TIM3_CH1, TIM1_BKIN, TIM16_CH1, COMP1_OUT, EVENTOUT; additional function ADC_IN6.
23 PA7 bidirectional 5 V-tolerant TTa I/O directly connected to the ADC; alternate functions SPI1_MOSI, I2S1_SD, TIM3_CH2, TIM14_CH1, TIM1_CH1N, TIM17_CH1, COMP2_OUT, EVENTOUT; additional function ADC_IN7.
24 PC4 bidirectional 5 V-tolerant TTa I/O directly connected to the ADC; alternate function EVENTOUT (printed as EVENTOU in the pin table), additional function ADC_IN14.
25 PC5 bidirectional 5 V-tolerant TTa I/O directly connected to the ADC; additional functions ADC_IN15 and WKUP5.
26 PB0 bidirectional 5 V-tolerant TTa I/O directly connected to the ADC; alternate functions TIM3_CH3, TIM1_CH2N, EVENTOUT; additional function ADC_IN8.
27 PB1 bidirectional 5 V-tolerant TTa I/O directly connected to the ADC; alternate functions TIM3_CH4, TIM14_CH1, TIM1_CH3N; additional function ADC_IN9.
28 PB2 bidirectional 5 V-tolerant FT I/O with no alternate or additional functions listed for this pin.
29 PB10 bidirectional 5 V-tolerant FTf I/O with FM+ capability; alternate functions SPI2_SCK, I2S2_CK, I2C2_SCL, CEC, TIM2_CH3.
30 PB11 bidirectional 5 V-tolerant FTf I/O with FM+ capability; alternate functions USART3_RX, TIM2_CH4, EVENTOUT, I2C2_SDA as printed.
31 VSS power_in Ground reference pin.
32 VDD power_in Digital power supply, 1.8 to 5.5 V.
33 PB12 bidirectional 5 V-tolerant FT I/O; alternate functions TIM1_BKIN, TIM15_BKIN, SPI2_NSS, I2S2_WS, EVENTOUT.
34 PB13 bidirectional 5 V-tolerant FTf I/O with FM+ capability; alternate functions SPI2_SCK, I2S2_CK, I2C2_SCL, TIM1_CH1N.
35 PB14 bidirectional 5 V-tolerant FTf I/O with FM+ capability; alternate functions SPI2_MISO, I2S2_MCK, I2C2_SDA, TIM1_CH2N, TIM15_CH1.
36 PB15 bidirectional 5 V-tolerant FT I/O; alternate functions SPI2_MOSI, I2S2_SD, TIM1_CH3N, TIM15_CH1N, TIM15_CH2; additional functions WKUP7, RTC_REFIN.
37 PC6 bidirectional 5 V-tolerant FT I/O supplied by VDDIO2 per datasheet note 4; alternate function TIM3_CH1.
38 PC7 bidirectional 5 V-tolerant FT I/O supplied by VDDIO2 per datasheet note 4; alternate function TIM3_CH2.
39 PC8 bidirectional 5 V-tolerant FT I/O supplied by VDDIO2 per datasheet note 4; alternate function TIM3_CH3.
40 PC9 bidirectional 5 V-tolerant FT I/O supplied by VDDIO2 per datasheet note 4; alternate function TIM3_CH4.
41 PA8 bidirectional 5 V-tolerant FT I/O supplied by VDDIO2 per datasheet note 4; alternate functions USART1_CK, TIM1_CH1, EVENTOUT, MCO, CRS_SYNC; additional function I2S2EXT_SD.
42 PA9 bidirectional 5 V-tolerant FT I/O supplied by VDDIO2 per datasheet note 4; alternate functions USART1_TX, TIM1_CH2, TIM15_BKIN, I2C1_SCL, MCO.
43 PA10 bidirectional 5 V-tolerant FT I/O supplied by VDDIO2 per datasheet note 4; alternate functions USART1_RX, TIM1_CH3, TIM17_BKIN, I2C1_SDA.
44 PA11 bidirectional 5 V-tolerant FT I/O, powered by VDD in the default version per note 1 (VDDIO2 supply requires customization); alternate functions USART1_CTS, TIM1_CH4, COMP1_OUT, EVENTOUT, I2C2_SCL.
45 PA12 bidirectional 5 V-tolerant FT I/O, powered by VDD in the default version per note 1 (VDDIO2 supply requires customization); alternate functions USART1_RTS, TIM1_ETR, COMP2_OUT, EVENTOUT, I2C2_SDA.
46 PA13 bidirectional 5 V-tolerant FT I/O supplied by VDDIO2 per note 4; alternate functions IR_OUT and SWDIO, with SWDIO and its internal pull-up active after reset per note 6.
47 VSS power_in Ground reference pin.
48 VDDIO2 power_in Digital I/O supply for the VDDIO2-powered pins, specified at 1.65 to 5.5 V in the electrical table.
49 PA14 bidirectional 5 V-tolerant FT I/O supplied by VDDIO2 per note 4; alternate functions USART2_TX and SWCLK, with SWCLK and its internal pull-down active after reset per note 6.
50 PA15 bidirectional 5 V-tolerant FT I/O supplied by VDDIO2 per note 4; alternate functions SPI1_NSS, I2S1_WS, USART2_RX, TIM2_CH1_ETR, EVENTOUT.
51 PC10 bidirectional 5 V-tolerant FT I/O supplied by VDDIO2 per note 4; no alternate functions listed for this pin in the pin table.
52 PC11 bidirectional 5 V-tolerant FT I/O supplied by VDDIO2 per note 4; no alternate functions listed for this pin in the pin table.
53 PC12 bidirectional 5 V-tolerant FT I/O supplied by VDDIO2 per note 4; no alternate functions listed for this pin in the pin table.
54 PD2 bidirectional 5 V-tolerant FT I/O supplied by VDDIO2 per note 4; alternate function TIM3_ETR.
55 PB3 bidirectional 5 V-tolerant FT I/O; alternate functions SPI1_SCK, I2S1_CK, TIM2_CH2, EVENTOUT.
56 PB4 bidirectional 5 V-tolerant FT I/O; alternate functions SPI1_MISO, I2S1_MCK, TIM17_BKIN, TIM3_CH1, EVENTOUT.
57 PB5 bidirectional 5 V-tolerant FT I/O; alternate functions SPI1_MOSI, I2S1_SD, I2C1_SMBA, TIM16_BKIN, TIM3_CH2; additional function WKUP6.
58 PB6 bidirectional 5 V-tolerant FTf I/O with FM+ capability; alternate functions I2C1_SCL, USART1_TX, TIM16_CH1N.
59 PB7 bidirectional 5 V-tolerant FTf I/O with FM+ capability; alternate functions I2C1_SDA, USART1_RX, TIM17_CH1N.
60 PF11-BOOT0 bidirectional 5 V-tolerant FT I/O that serves as the boot memory selection pin (BOOT0) at startup, with the boot pin shareable with GPIO if disabled by the boot select option bit.
61 PB8 bidirectional 5 V-tolerant FTf I/O with FM+ capability; alternate functions I2C1_SCL, CEC, TIM16_CH1.
62 PB9 bidirectional 5 V-tolerant FTf I/O with FM+ capability; alternate functions SPI2_NSS, I2S2_WS, I2C1_SDA, IR_OUT, TIM17_CH1, EVENTOUT.
63 VSS power_in Ground reference pin.
64 VDD power_in Digital power supply, 1.8 to 5.5 V.

Key specifications

Parameter Value
Manufacturer Flashchip Microelectronics
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Internal AHB clock frequency fHCLK 0 100 MHz 37
Internal APB clock frequency fPCLK 0 100 MHz 37
Standard operating voltage VDD 1.8 5.5 V 37
I/O supply voltage VDDIO2 1.65 5.5 V 37
Analog operating voltage VDDA 5.5 V 37
Backup operating voltage VBAT 2.1 5.5 V 37
I/O input voltage VIN -0.3 V TC and RST I/O 37
I/O input voltage VIN -0.3 5.5 V FT and FTf I/O 37
Ambient temperature for the suffix 6 version TA -40 85 C Suffix 6 version; maximum power dissipation 37
Ambient temperature for the suffix 6 version TA -40 105 C Suffix 6 version; low power dissipation 37
Junction temperature range TJ -40 105 C Suffix 6 version 37
VDD fall time rate tVDD 20 us/V 37
VDDA fall time rate tVDDA 20 us/V 37
External main supply voltage VDD-VSS -0.3 5.8 V 36
External I/O supply voltage VDDIO2-VSS -0.3 5.8 V 36
External analog supply voltage VDDA-VSS -0.3 5.8 V 36
Allowed voltage difference for VDD>VDDA VDD-VDDA 0.3 V 36
External backup supply voltage VBAT-VSS -0.3 5.8 V 36
Input voltage on TTa pins VIN 5.8 V 36
Input voltage on any other pins VIN 5.8 V 36
Variations between different VDD power pins /△VDDx/ 50 mV 36
Variations between all the different ground pins /VSSx-VSS/ 50 mV 36
Electrostatic discharge voltage (HBM) VESD(HBM) 3000 V 37
Power on/down reset threshold VPOR/PDR 1.51 1.58 1.65 V Falling edge 38
Power on/down reset threshold VPOR/PDR 1.54 1.62 1.7 V Rising edge 38
Reset temporization tRSTTEMPO 1.5 2.5 4.5 ms 38
PVD threshold 0 VPVD0 1.59 1.67 1.75 V Falling edge 38
PVD threshold 0 VPVD0 1.75 1.83 1.91 V Rising edge 38
PVD threshold 1 VPVD1 1.75 1.83 1.91 V Falling edge 38
PVD threshold 1 VPVD1 1.9 1.98 2.06 V Rising edge 38
PVD threshold 2 VPVD2 1.9 1.98 2.06 V Falling edge 38
PVD threshold 2 VPVD2 2.06 2.14 2.22 V Rising edge 38
PVD threshold 3 VPVD3 2.06 2.14 2.22 V Falling edge 38
PVD threshold 3 VPVD3 2.21 2.29 2.37 V Rising edge 38
PVD threshold 4 VPVD4 2.21 2.29 2.37 V Falling edge 38
PVD threshold 4 VPVD4 2.35 2.43 2.51 V Rising edge 38
PVD threshold 5 VPVD5 2.35 2.43 2.51 V Falling edge 38
PVD threshold 5 VPVD5 2.49 2.57 2.65 V Rising edge 38
PVD threshold 6 VPVD6 2.49 2.57 2.65 V Falling edge 38
PVD threshold 6 VPVD6 2.64 2.72 2.8 V Rising edge 38
PVD threshold 7 VPVD7 2.64 2.72 2.8 V Falling edge 38
PVD threshold 7 VPVD7 2.8 2.88 2.96 V Rising edge 38
Internal reference voltage VREFINT 1.22 1.23 1.24 V -40C<TA<+105 38
ADC_IN17 buffer startup time tSTART 10 us 38
ADC sampling time when reading the internal reference voltage tS_vrefint 8 us 38
Internal reference voltage spread over the temperature range △VREFINNT 10 mV VDDA=3V 38
Temperature coefficient TCoeff 100 ppm/C 38
User external clock source frequency fHSE_EXT 8 32 MHz 39
OSC_IN high or low time tW(HSEH), tW(HSEL) 15 ns 39
OSC_IN rise or fall time tr(HSE), tf(HSE) 20 ns 39
User external clock source frequency (LSE) fLSE_EXT 32.768 1000 KHz 39
Oscillator frequency fOSC_IN 4 8 20 MHz 39
Accuracy of the HSI48 oscillator (factory calibrated) ACCHSI48 -1.84 2 % TA=-40 to 105 @SS 40
Accuracy of the HSI48 oscillator (factory calibrated) ACCHSI48 -1.58 1.76 % TA=-40 to 105 @TT 40
Accuracy of the HSI48 oscillator (factory calibrated) ACCHSI48 -1.24 1.72 % TA=-40 to 105 @FF 40
LSI frequency fLSI 31.9 40 55.5 KHz 40
PLL input clock fPLL_IN 1 8 24 MHz 40
PLL multiplier output clock tPLL_OUT 16 72 MHz 40
Injected current IINJ -5 5 mA 42

CAD (KiCad official)

  • Symbol: FCM32F051R8T6
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: fcm32f051r8t6-etched.step / fcm32f051r8t6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); fcm32f051r8t6.step / fcm32f051r8t6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Flashchip Microelectronics datasheet (56 pp, sha256 2d64a6b3447de354, retrieved 2026-10-20, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF