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FAN73912MX

Public Made by Adom

by adom

onsemi Gate Drivers, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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FAN73912MX

onsemi · Gate Drivers · SOIC-16-300mil

FAN73912MX from onsemi, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LO output Low-side driver output, typically sourcing 2 A and sinking 3 A.
2 COM power_in Low-side driver return and the reference for voltage parameters unless stated otherwise (Table 2).
3 VCC power_in Low-side supply voltage, recommended 12 V to 20 V with an absolute maximum of 25 V (Tables 2 and 3).
4 NC unconnected No connection.
5 NC unconnected No connection.
6 VS power_in High-voltage floating supply return (offset), with an absolute range of VB − 25 V to VB + 0.3 V and a dVS/dt limit of ±50 V/ns (Table 2).
7 VB power_in High-side floating supply, recommended VS + 12 V to VS + 20 V (Table 3).
8 HO output High-side driver output, typically sourcing 2 A and sinking 3 A.
9 NC unconnected No connection.
10 NC unconnected No connection.
11 VDD power_in Logic supply voltage, recommended VSS + 3 V to VSS + 20 V (Table 3).
12 HIN input Logic input for the high-side gate driver output; pulses shorter than the input filter time (tFLTIN, 80 to 220 ns) are rejected.
13 SD input Logic shutdown input; drive HIGH to shut down the gate driver, with a shutdown propagation delay of 260 to 400 ns.
14 LIN input Logic input for the low-side gate driver output; pulses shorter than the input filter time (tFLTIN, 80 to 220 ns) are rejected.
15 VSS power_in Logic ground, recommended −10 V to +10 V referenced to COM (Table 3).
16 NC unconnected No connection.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-16-300mil
Category Motor Driver ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High-Side Floating Supply Voltage VB -0.3 1225 V 4
Low-Side Supply Voltage VCC -0.3 25 V 4
Logic Supply Voltage (second row) VDD -0.3 25 V 4
Logic Input Voltage (HIN, LIN, SD) (second row) VIN -0.3 25 V 4
Low-Side Floating Output Voltage VLO -0.3 V 4
Allowable Offset Voltage Slew Rate dVS/dt -50 50 V/ns 4
Power Dissipation PD 1.3 W Note 2, 3, 4 4
Thermal Resistance, Junction to Ambient JA 95 °C/W 4
Junction Temperature TJ 150 °C 4
Storage Temperature TSTG -55 150 °C 4
Low-Side Supply Voltage VCC 12 20 V 4
Low-Side (LO) Output Voltage VLO 0 V 4
Logic Supply Voltage (second row) VDD 0 20 V 4
Logic Ground VSS -10 10 V Note 5 4
Logic Input Voltage (HIN, LIN, SD) (second row) VIN 0 20 V 4
Junction Temperature TJ -40 125 °C 4
High-Side Floating Supply Offset Voltage VS 1200 V Note 6 4
Quiescent VCC Supply Current IQCC 170 300 µA VIN = 0 V or VDD 5
Quiescent VDD Supply Current IQDD 10 µA VIN = 0 V or VDD 5
Operating VCC Supply Current IPCC 650 950 µA fIN = 20 kHz, rms VIN = 15 VPP 5
Shutdown Supply Current ISD 30 50 µA SD = VDD 5
VCC Supply Under-Voltage Positive-Going Threshold Voltage VCCUV+ 9.7 11 12 V VCC = Sweep 5
VCC Supply Under-Voltage Negative-Going Threshold Voltage VCCUV- 9.2 10.5 11.4 V VCC = Sweep 5
Quiescent VBS Supply Current IQBS 50 100 µA VIN = 0 V or VDD 5
Operating VBS Supply Current IPBS 550 850 µA fIN = 20 kHz, rms value 5
VBS Supply Under-Voltage Positive-Going Threshold Voltage VBSUV+ 9.7 11 12 V VBS = Sweep 5
VBS Supply Under-Voltage Negative-Going Threshold Voltage VBSUV- 9.2 10.5 11.4 V VBS = Sweep 5
Offset Supply Leakage Current ILK 50 µA VB = VS = 1200 V (TJ = 25°C) 5
Offset Supply Leakage Current ILK 100 µA VB = VS = 1200 V (TJ = 125°C) (Note 7) 5
Logic 1 Input Voltage VIH 2.4 V VDD = 3 V 5
Logic 1 Input Voltage VIH 9.5 V VDD = 15 V 5
Logic 0 Input Voltage VIL 0.8 V VDD = 3 V 5
Logic 0 Input Voltage VIL 6 V VDD = 15 V 5
Logic 1 Input Bias Current IIN+ 30 50 µA VIN = 15 V 5
Logic 0 Input Bias Current IIN- 1 µA VIN = 0 V 5
High-Level Output Voltage, VBIAS-VO VOH 1.2 V IO = 0 A 5
Low-Level Output Voltage, VO VOL 0.1 V IO = 0 A 5
Allowable Negative VS Pin Voltage for HIN Signal Propagation to HO -9.8 -7 V 5
Input Filtering Time (HIN, LIN) tFLTIN 80 150 220 ns Note 8 6
Shutdown Propagation Delay Time tSD 260 330 400 ns 6
Delay Matching, HO & LO Turn-On/OFF MT 50 ns HO & LO turn-on/off (Note 10) 6
Output Pulse-Width Matching PM 50 100 ns PWIN > 1 s (Note 11) 6

CAD (KiCad official)

  • Symbol: FAN73912MX
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: fan73912mx-etched.step / fan73912mx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); fan73912mx.step / fan73912mx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (20 pp, sha256 6724dba33ffc960f, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF