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FAN7385MX

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onsemi Gate Drivers, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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FAN7385MX

onsemi · Gate Drivers · SOP-14

FAN7385MX from onsemi, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Low-side and fixed logic supply, recommended 10 V to 20 V, absolute maximum -0.3 V to 25 V.
2 NC unconnected No connection.
3 IN1 input Channel 1 control input, compatible with 3.3 V and 5 V logic levels, with VIH of 2.5 V and VIL of 1.3 V and an internal 500 kΩ pull-down.
4 NC unconnected No connection.
5 IN2 input Channel 2 control input, compatible with 3.3 V and 5 V logic levels, with VIH of 2.5 V and VIL of 1.3 V and an internal 500 kΩ pull-down.
6 NC unconnected No connection.
7 GND power_in Logic ground reference for the control inputs and VDD supply.
8 VS2 power_in Channel 2 floating supply return; allowed to swing with dVS/dt up to 50 V/ns and is rated up to 600 V.
9 HO2 output Channel 2 high-side gate drive output, typically 350 mA source and 650 mA sink, in phase with IN2.
10 VB2 power_in Channel 2 floating high-side supply, recommended VS+10 V to VS+20 V, absolute maximum -0.3 V to 625 V, with UVLO protection.
11 NC unconnected No connection.
12 VS1 power_in Channel 1 floating supply return; allowed to swing with dVS/dt up to 50 V/ns and is rated up to 600 V.
13 HO1 output Channel 1 high-side gate drive output, typically 350 mA source and 650 mA sink, in phase with IN1.
14 VB1 power_in Channel 1 floating high-side supply, recommended VS+10 V to VS+20 V, absolute maximum -0.3 V to 625 V, with UVLO protection.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOP-14
Category Motor Driver ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High-side floating supply voltage VB1, VB2 (absolute maximum) VB -0.3 625 V 6
Low-side and fixed logic supply voltage VDD (absolute maximum) VDD -0.3 25 V 6
Allowed offset voltage slew rate dVS/dt dVS/dt 50 V/ns 6
Power dissipation PD PD 1 W Footnotes 2, 3, 4 apply 6
Junction temperature TJ TJ 150 °C 6
Storage temperature TS TS 150 °C 6
High-side offset voltage VS1, VS2 (recommended) VS 600 V Minimum printed as 6-VDD 6
Low-side and fixed logic supply voltage VDD (recommended) VDD 10 20 V 6
Ambient temperature TA (recommended) TA -40 125 °C 6
VBS1 and VBS2 supply undervoltage positive threshold VBSUV+ 8.2 9.1 10.2 V VBS1=VBS2=sweep 7
VBS1 and VBS2 supply undervoltage negative threshold VBSUV- 7.6 8.5 9.6 V VBS1=VBS2=sweep 7
Offset supply leakage current ILK 10 μA VB=VS=600V 7
VO high-level short-circuit pulsed output current IO+ IO+ 250 350 mA VO=0 V, VIN=5 V, PW<10 µs 7
VO low-level short-circuit pulsed output current IO- IO- 500 650 mA VO=15 V, VIN=0 V, PW<10 µs 7
Allowed negative VS pin voltage for signal propagation to HO VS -9.8 -7 V 7
Logic 1 input voltage VIH 2.5 V 7
Logic 0 input voltage VIL 1.3 V 7
Logic 0 input bias current IIN- 2 μA VIN=0V 7
Logic 1 input bias current IIN+ 10 20 μA VIN=5V 7
Input pull-down resistance RIN 400 500 600 KΩ 7
High-level output voltage, VBIAS-VO VOH 30 mV IO=0 mA (no load) 7
Low-level output voltage, VO VOL 30 mV IO=0 mA (no load) 7
Turn-on propagation delay ton 110 180 ns VS=0V 7
Turn-off propagation delay toff 110 180 ns VS=0 V or 600 V 7
Turn-on rise time tr 50 90 ns 7
Turn-off fall time tf 30 70 ns 7
VDD quiescent supply current IQDD 28 50 μA VIN1=VIN2=0 V or 5 V 7
VDD operating supply current IPDD 35 70 μA fIN1=fIN2=10kHz, rms value 7
VBS1 and VBS2 quiescent supply current IQBS1,2 50 85 μA VIN1=0 V or 5 V 7
VBS1 and VBS2 operating supply current IPBS1,2 220 300 μA fIN1=10 kHz, rms value 7
VBS1 and VBS2 undervoltage lockout hysteresis VBSHYS 0.6 V VBS1=VBS2=sweep 7
Junction-to-ambient thermal resistance θJA θJA 110 °C/W 6
Delay matching, channels 1 and 2, turn-on/turn-off MT 0 ns 7

CAD (KiCad official)

  • Symbol: FAN7385MX
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: fan7385mx-etched.step / fan7385mx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); fan7385mx.step / fan7385mx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (17 pp, sha256 470d067e2f901c5f, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF