component

FAN7384MX

Public Made by Adom

by adom

onsemi Gate Drivers, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentmotor driver icsfan7384mxfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

FAN7384MX

onsemi · Gate Drivers · SOP-14

FAN7384MX from onsemi, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LIN input Logic input for the low-side gate driver, compatible with 3.3 V and 5 V logic (VIH 2.5 V, VIL 1.2 V) and limited to the GND to VDD range.
2 SD input Active-low shutdown control input that turns off both gate outputs; its input range is GND to VDD.
3 HIN input Logic input for the high-side gate driver, compatible with 3.3 V and 5 V logic (VIH 2.5 V, VIL 1.2 V) and limited to the GND to VDD range.
4 VDD power_in Low-side and fixed logic supply voltage, recommended 13 V to 20 V, with an absolute maximum of 25 V.
5 FO bidirectional Open-drain bidirectional fault pin, with a voltage range of -0.3 V to VDD+0.3 V.
6 CSC input Short-circuit current sense input compared against an internal 0.5 V reference (0.47 V to 0.53 V), with an input range of -0.3 V to VDD+0.3 V.
7 GND power_in Ground reference for the logic inputs and the low-side driver; logic inputs and outputs are referenced to GND.
8 VSL power_in Low-side source (current-sense return) connection, with a tolerance of -7 V to +7 V relative to GND.
9 LO output Low-side gate driver output, swinging between GND and VDD.
10 NC unconnected No connection.
11 NC unconnected No connection.
12 VS power_in High-side floating supply offset; VS may range from VB-25 V to VB+0.3 V, with a maximum slew rate of 50 V/ns.
13 HO output High-side floating gate driver output, swinging between VS and VB.
14 VB power_in High-side floating supply, recommended VS+13 V to VS+20 V, with an absolute maximum of 625 V.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOP-14
Category Motor Driver ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDD static supply current IQDD 600 800 µA VLIN = 0 V or 5 V 7
VDD operating supply current IPDD 950 1300 µA fLIN = 20 kHz, rms 7
VDD UVLO positive-going threshold VDDUV+ 10.9 11.9 12.9 V VDD swept 7
VDD UVLO negative-going threshold VDDUV- 10.4 11.4 12.4 V VDD swept 7
VBS UVLO positive-going threshold VBSUV+ 10.6 11.5 12.4 V VBS swept 7
VBS UVLO negative-going threshold VBSUV- 10.1 11 11.9 V VBS swept 7
Offset supply leakage current ILK 10 µA VB = VS = 600 V 7
VBS static supply current IQBS 50 90 µA VHIN = 0 V or 5 V 7
VBS operating supply current IPBS 400 600 µA fHIN = 20 kHz, rms 7
High-level output voltage, VBIAS - VO VOH 100 mV IO = 0 mA (no load) 7
Low-level output voltage, VO VOL 100 mV IO = 0 mA (no load) 7
Output high short-circuit pulsed current IO+ 200 250 mA VO = 0 V, VIN = 5 V, PW < 10 µs 7
Output low short-circuit pulsed current IO- 420 500 mA VO = 15 V, VIN = 0 V, PW < 10 µs 7
Allowable negative VS pin voltage at HO signal propagation VS -9.8 -7 V 7
VSL-GND / GND-VSL withstand voltage VSL-GND -7 7 V 7
Logic '1' input voltage (HIN, LIN) VIH 2.5 V 7
Logic '0' input voltage (HIN, LIN) VIL 1.2 V 7
Logic '1' input bias current IIN+ 10 15 20 µA VIN = 5 V 7
Logic '0' input bias current IIN- 2 µA VIN = 0 V 7
Short-circuit detector reference voltage VCSCREF 0.47 0.5 0.53 V 8
Short-circuit input current ICSCIN 5 10 15 µA VCSCIN = 1 V, RCSCIN = 100K 8
Soft-off source current ISOFT 5 10 15 mA VDD = 15 V 8
CSC pin negative voltage withstand -VCSC -12 V CSC pin voltage -12 V, time < 2 s 8
CSC pin negative voltage withstand -VCSC -20 V 8
Fault input high-level voltage VFINH 2.5 V 8
Fault input low-level voltage VFINL 1.2 V 8
Fault output high-level voltage VFOH 4.7 V VCSC = 0 V, RPULL-UP = 4.7K 8
Fault output low-level voltage VFOL 0.8 V VCSC = 1 V, IFO = 2 mA 8
Fault output pulse width tFO 60 100 µs VCSCIN = 1 V 8
Turn-on propagation delay ton 180 260 ns VS = 0 V 8
Turn-off propagation delay toff 170 240 ns VS = 0 V or 600 V 8
Turn-on rise time tr 50 100 ns 8
Turn-off fall time tf 30 80 ns 8
Dead time DT 80 120 170 ns 8
VS recommended floating supply offset voltage VS 600 V 6
VDD supply voltage (recommended) VDD 13 20 V 6
Ambient temperature (recommended) TA -40 125 °C 6
Floating supply voltage VB (absolute) VB -0.3 625 V 6
Low-side supply voltage VDD (absolute) VDD -0.3 25 V 6
Logic input voltage HIN, LIN, SD (absolute) VIN -0.3 V 6
Current sense input voltage (absolute) VCSC -0.3 V 6
Allowable offset supply voltage transition rate dVS/dt 50 V/ns 6
Power dissipation PD 1 W 6
Junction temperature TJ 150 °C 6
Storage temperature TS -55 150 °C 6
Junction-to-ambient thermal resistance θJA 110 °C/W Mounted on 76.2 x 114.3 x 1.6 mm FR-4 PCB (notes 2-3, JESD51-2/-3) 6
Logic '1' input... high-level delay matching MT 50 ns 8
Undervoltage fault delay tUVFLT 16 µs 8
CSC pin fault delay tCSCFLT 300 ns 8
CSC trigger to FO delay tCSCFO 350 ns 8
CSC trigger to low-side gate output delay tCSCLO 600 ns From VCSC = 1 V to start of gate turn-off 8
Shutdown to FO propagation delay tSDFO 60 ns 8
Shutdown to high/low gate turn-off tSDOFF 100 ns 8
VDD UVLO hysteresis VDDHYS 0.5 V VDD swept 7
VBS UVLO hysteresis VBSHYS 0.5 V VBS swept 7
Shutdown '1' input voltage SD+ 1.2 V 7
Shutdown '0' input voltage SD- 2.5 V 7
Logic input hysteresis VINHYS 0.5 V 7
Fault input hysteresis VFINHYS 0.5 V 8

CAD (KiCad official)

  • Symbol: FAN7384MX
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: fan7384mx-etched.step / fan7384mx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); fan7384mx.step / fan7384mx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (19 pp, sha256 1d6d396f00c8be7a, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF