# FAN7171MX-F085

**onsemi** · Gate Drive ICs · SOIC-8

FAN7171MX-F085 from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Low-side and logic supply voltage, recommended 10 V to 20 V, with an internal 25 V shunt regulator (VSHUNT 23 V to 25 V at 5 mA) and an absolute maximum of VSHUNT. |
| 2 | IN | input | Logic input for the high-side gate driver output, with recommended range GND to VDD, VIH minimum 2.5 V, VIL maximum 0.8 V, and an internal 40 kΩ to 110 kΩ pull-down. |
| 3 | NC | unconnected | No connection; leave unconnected. |
| 4 | GND | power_in | Ground reference for the logic input and VDD supply, with the IN input levels referenced to GND. |
| 5 | NC | unconnected | No connection; leave unconnected. |
| 6 | VS | power_in | High-voltage floating supply return (high-side offset), rated for up to 600 V DC offset and dVS/dt of ±50 V/ns, with VBS to be kept VS+10 V to VS+20 V. |
| 7 | HO | output | High-side driver output, which swings between VS and VB with 4 A typical sourcing and sinking pulsed current (PW ≤ 10 µs) and VOL of 35 mV maximum at no load. |
| 8 | VB | power_in | High-side floating supply, recommended VS+10 V to VS+20 V, with absolute maximum 625 V and UVLO thresholds of 8.2 V to 10.2 V (rising) and 7.5 V to 9.5 V (falling). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | Power Management ICs |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High-Side Floating Supply Voltage (VB) | VB | -0.3 |  | 625 | V | Note 3 | 3 |
| Low-Side and Logic Supply Voltage (VDD) | VDD | -0.3 |  |  | V | Note 3 | 3 |
| Allowable Offset Voltage Slew Rate | dVS/dt | -50 |  | 50 | V/ns |  | 3 |
| Power Dissipation | PD |  |  | 0.625 | W | Notes 4, 5, 6 | 3 |
| Thermal Resistance | θJA |  |  | 200 | °C/W |  | 3 |
| Junction Temperature | TJ | -55 |  | 150 | °C |  | 3 |
| Storage Temperature | TSTG | -55 |  | 150 | °C |  | 3 |
| Operating Ambient Temperature | TA | -40 |  | 125 | °C |  | 3 |
| ESD Human Body Model (HBM) | ESD |  |  | 2000 | V | Human Body Model (HBM) | 3 |
| ESD Charge Device Model (CDM) | ESD |  |  | 500 | V | Charge Device Model (CDM) | 3 |
| Supply Voltage (VDD) | VDD | 10 |  | 20 | V |  | 3 |
| Minimum Input Pulse Width | TPULSE | 80 |  |  | ns | Note 7 | 3 |
| Quiescent VDD Supply Current | IQDD | 25 |  | 70 | μA | VIN = 0 V or 5 V | 4 |
| Operating VDD Supply Current | IPDD | 35 |  | 100 | μA | fIN = 20 kHz, No Load | 4 |
| VBS Supply Under-Voltage Positive-Going Threshold Voltage | VBSUV+ | 8.2 | 9.2 | 10.2 | V | VBS = Sweep | 4 |
| VBS Supply Under-Voltage Negative-Going Threshold Voltage | VBSUV− | 7.5 | 8.5 | 9.5 | V | VBS = Sweep | 4 |
| VBS Supply UVLO Hysteresis Voltage | VBSHYS |  | 0.6 |  | V | VBS = Sweep | 4 |
| Offset Supply Leakage Current | ILK |  |  | 50 | μA | VB = VS = 600 V | 4 |
| Quiescent VBS Supply Current | IQBS | 60 |  | 120 | μA | VIN = 0 V or 5 V | 4 |
| Operating VBS Supply Current | IPBS | 0.73 |  | 2.8 | mA | CLOAD = 1 nF, fIN = 20 kHz, RMS Value | 4 |
| VDD and VBS Shunt Regulator Clamping Voltage | VSHUNT | 23 |  | 25 | V | ISHUNT = 5 mA | 4 |
| Logic "1" Input Voltage | VIH | 2.5 |  |  | V |  | 4 |
| Logic "0" Input Voltage | VIL |  |  | 0.8 | V |  | 4 |
| Logic Input High Bias Current | IIN+ | 45 |  | 125 | μA | VIN = 5 V | 4 |
| Logic Input Low Bias Current | IIN− |  |  | 2 | μA | VIN = 0 V | 4 |
| Input Pull-down Resistance | RIN | 40 |  | 110 | kΩ |  | 4 |
| High Level Output Voltage (VBIAS − VO) | VOH |  |  | 1.5 | V | No Load | 4 |
| Low Level Output Voltage | VOL |  |  | 35 | mV | No Load | 4 |
| Output High, Short-Circuit Pulsed Current | IO+ | 3 |  | 4 | A | VHO = 0 V, VIN = 5 V, PW ≤ 10 μs | 4 |
| Output Low, Short-Circuit Pulsed Current | IO− | 3 |  | 4 | A | VHO = 15 V, VIN = 0 V, PW ≤ 10 μs | 4 |
| Allowable Negative VS Pin Voltage for IN Signal Propagation to HO | VS | -9.8 |  | -7 | V |  | 4 |
| Turn-On Propagation Delay | tON | 150 |  | 210 | ns | VS = 0 V | 4 |
| Turn-Off Propagation Delay | tOFF | 150 |  | 210 | ns | VS = 0 V | 4 |
| Turn-On Rise Time | tR | 25 |  | 50 | ns |  | 5 |
| Turn-Off Fall Time | tF | 15 |  | 45 | ns |  | 5 |

## CAD (KiCad official)

- Symbol: `FAN7171MX-F085`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `fan7171mx-f085-etched.step` / `fan7171mx-f085-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `fan7171mx-f085.step` / `fan7171mx-f085.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [onsemi datasheet](https://www.onsemi.cn/pdf/datasheet/fan7171_f085-d.pdf) (11 pp, sha256 `01bb7ca1d74bb82d`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/fan7171mx-f085-datasheet.pdf)