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FAN6921MRMY

Public Made by Adom

by adom

onsemi AC-DC Controllers And Regulators, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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FAN6921MRMY

onsemi · AC-DC Controllers And Regulators · SOP-16

FAN6921MRMY from onsemi, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RANGE passive RANGE pin impedance changes with the VIN pin voltage: high impedance when VIN is below its threshold and low impedance when VIN is high.
2 COMP output Transconductance error-amplifier output for PFC voltage feedback, with a simple compensation circuit connected between this pin and GND.
3 INV input Inverting input of the PFC error amplifier, receiving the PFC voltage through a divider and providing PFC output over- and under-voltage protection.
4 CSPFC input PFC over-current sense input that turns off the PFC switch when the sensed voltage reaches the internal 0.82 V typical threshold, giving cycle-by-cycle current limiting.
5 CSPWM input PWM current-sense input for cycle-by-cycle current limiting, current-mode control and high/low line over-power compensation, fed through a resistor in the PWM switch current path.
6 OPFC output Totem-pole driver output for the external PFC power MOSFET, with a clamped gate output voltage of 15.5 V.
7 VDD power_in Power supply pin with startup and turn-off thresholds of 18 V and 7.5 V, startup current below 30 µA and operating current below 10 mA.
8 OPWM output Totem-pole driver output for the external PWM power MOSFET, with a clamped gate output voltage of 17.5 V.
9 GND power_in Power ground and signal ground reference for the controller; all voltages are referenced to this pin.
10 DET input Auxiliary-winding divider input used for over-power offset, valley detection, and output OVP, which latches the controller when the flat voltage exceeds 2.5 V.
11 FB input Feedback input from the opto-coupler with about 5 kΩ input impedance; FB above about 4.2 V for more than 50 ms activates open-loop, overload and output-short protection.
12 RT input Adjustable over-temperature and external latch-trigger input, with a constant current flowing out of the pin; latch protection activates when RT falls below 0.8 V typical.
13 VIN power_in Line-voltage sense input, received through a voltage divider, for brown-in/out protection and for controlling the RANGE pin.
14 ZCD input Zero-current detection input from the PFC inductor auxiliary winding; pulling it below 0.2 V typical disables PFC switching.
15 NC unconnected No connection.
16 HV power_in High-voltage startup pin tied to the AC line through a resistor (100 kΩ typical) to charge the VDD capacitor; absolute maximum rating is 500 V.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOP-16
Category Power Management (PMIC)
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage VDD 30 V 7
HV pin voltage VHV 500 V 7
OPFC, OPWM output voltage VH -0.3 25 V 7
Others (INV, COMP, CSPFC, DET, FB, CSPWM, RT) VL -0.3 7 V 7
Input Voltage to ZCD Pin VZCD -0.3 12 V 7
Power Dissipation PD 800 mW 7
Thermal Resistance (Junction-to-Air) θJA 104 °C/W 7
Thermal Resistance (Junction-to-Case) θJC 41 °C/W 7
Operating Junction Temperature TJ -40 150 °C 7
Storage Temperature Range TSTG -55 150 °C 7
Lead Temperature (Soldering 10 Seconds) TL 260 °C 7
ESD Human Body Model 4500 V JESD22-A114, all pins except HV pin 7
ESD Charged Device Model 1250 V JESD22-C101, all pins except HV pin 7
Operating Ambient Temperature TA -40 105 °C 7
Turn-On Threshold Voltage VDD-ON 16.5 18 19.5 V 8
PWM Off Threshold Voltage VDD-PWM-OFF 9 10 11 V 8
Turn-Off Threshold Voltage VDD-OFF 6.5 7.5 8.5 V 8
Operating Current at PWM-Off Phase IDD-PWM-OFF 70 120 170 µA VDD=VDD-PWM-OFF - 0.5 V 8
VDD Over-Voltage Protection (Latch-Off) VDD-OVP 26.5 27.5 28.5 V 8
VDD OVP Debounce Time tVDD-OVP 100 150 200 µs 8
Under-Voltage Protection Threshold Voltage for AC Input VVIN-UVP 0.95 1 1.05 V 8
Under-Voltage Protection Debounce Time (No Need at Startup and Hiccup Mode) tVIN-UVP 70 100 130 ms 8
High VVIN Threshold for RANGE Comparator VVIN-RANGE-H 2.4 2.45 2.5 V 8
Low VVIN Threshold for RANGE Comparator VVIN-RANGE-L 2.05 2.1 2.15 V 8
PFC Maximum On Time tON-MAX-PFC 22 25 28 µs RMOT=24 kΩ 8
Feedback Comparator Reference Voltage VREF 2.465 2.5 2.535 V 9
Clamp High Feedback Voltage VINV-H 2.7 2.75 2.8 V RANGE=Open 9
Clamp High Feedback Voltage VINV-H 2.6 2.65 2.7 V RANGE=Ground 9
Clamp Low Feedback Voltage VINV-L 2.25 2.35 2.45 V 9
Under-Voltage Protection for INV Input VINV-UVP 0.35 0.45 0.55 V 9
PWM and PFC Off Threshold for Brownout Protection VINV-BO 1.15 1.2 1.25 V 9
Limited Voltage on COMP Pin for Brownout Protection VCOMP-BO 1.55 1.6 1.65 V 9
PFC Gate Output Clamping Voltage VZ 14 15.5 17 V VDD= 25 V 10
Input Threshold Voltage Rising Edge VZCD 1.9 2.1 2.3 V VZCD Increasing 10
Threshold Voltage Hysteresis VZCD-HYST 0.25 0.35 0.45 V VZCD Decreasing 10
Lower Clamp Voltage VZCD-LOW 0.4 0.65 0.9 V 10
Restart Time (PFC) tRESTART-PFC 300 500 700 µs 10
Open-Loop Protection Threshold Voltage VFB-OLP 3.9 4.2 4.5 V 11
Debounce Time for Open Loop Protection tFB-OLP 40 50 60 ms 11
Comparator Reference Voltage (DET-OVP) VDET-OVP 2.45 2.5 2.55 V 11
Lower Clamp Voltage (DET) VDET-LOW 0.5 0.7 0.9 V IDET=1 mA 11
Maximum On Time (PWM) tON-MAX-PWM 38 45 52 µs 11
Minimum Off Time tOFF-MIN 7 8 9 µs VFB≧VN, TA=25°C 11
Beginning of Green-On Mode at FB Voltage Level VN 1.95 2.1 2.25 V 11
Beginning of Green-Off Mode at FB Voltage Level VG 1 1.15 1.3 V 11
PWM Gate Output Clamping Voltage VCLAMP 16 17.5 19 V VDD=25 V 12
The Limit Voltage on CSPWM Pin for Over Power Compensation VLIMIT 0.81 0.84 0.87 V IDET <75 µA, TA=25°C 12
The Limit Voltage on CSPWM Pin for Over Power Compensation VLIMIT 0.69 0.72 0.75 V IDET=185 µA, TA=25°C 12
The Limit Voltage on CSPWM Pin for Over Power Compensation VLIMIT 0.55 0.58 0.61 V IDET=350 µA, TA=25°C 12
The Limit Voltage on CSPWM Pin for Over Power Compensation VLIMIT 0.34 0.4 0.46 V IDET=550 µA, TA=25°C 12
Threshold Voltage on FB Pin for PFC Enable/Disable (PFC disable) VCTL-PFC-OFF 1.7 1.75 1.8 V RANGE Pin Internally Open 12
Threshold Voltage on FB Pin for PFC Enable/Disable (PFC disable) VCTL-PFC-OFF 1.6 1.65 1.7 V RANGE Pin Internally Ground 12
Threshold Voltage on FB Pin for PFC Disable to Enable VCTL-PFC-ON 1.85 1.9 1.95 V RANGE Pin Internally Open 12
Threshold Voltage on FB Pin for PFC Disable to Enable VCTL-PFC-ON 1.7 1.75 1.8 V RANGE Pin Internally Ground 12
PFC Disable Debounce Time tPFC-OFF 400 500 600 ms PFC Enable to Disable 12
PFC Enable Debounce Time tPFC-ON 2 2.5 3 ms PFC Disable to Enable 12
Internal Threshold Temperature for OTP TOTP 125 140 155 °C 13
Internal Source Current of RT Pin IRT 90 100 110 µA 13
Latch-Mode Triggering Voltage VRT-LATCH 0.75 0.8 0.85 V 13
Threshold Voltage for Two-level Debounce Time VRT-OTP-LEVEL 0.45 0.5 0.55 V 13

CAD (KiCad official)

  • Symbol: FAN6921MRMY
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: fan6921mrmy-etched.step / fan6921mrmy-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); fan6921mrmy.step / fan6921mrmy.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (25 pp, sha256 6ac9b44f496c1530, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF