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FAN6921BMRMY

Public Made by Adom

by adom

onsemi AC-DC Controllers And Regulators, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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FAN6921BMRMY

onsemi · AC-DC Controllers And Regulators · SOIC-16

FAN6921BMRMY from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RANGE output RANGE pin impedance follows the VIN pin voltage, set to high impedance when VIN is below its threshold and low impedance when VIN is high, with output low voltage of 0.5 V max at 1 mA.
2 COMP output Output of the transconductance error amplifier for PFC output voltage feedback, with a simple compensation network connected between this pin and GND.
3 INV input Inverting input of the error amplifier that receives the PFC voltage through a divider and provides PFC output over- and under-voltage protection.
4 CSPFC input PFC over-current comparator input; when the sensed voltage reaches the 0.82 V typical threshold, the PFC switch is turned off for cycle-by-cycle current limiting.
5 CSPWM input PWM over-current comparator input that senses the PWM switch current for cycle-by-cycle limiting, current-mode control with the FB pin, and line-dependent over-power compensation.
6 OPFC output Totem-pole driver output for the external PFC power MOSFET, with a clamped gate output voltage of 15.5 V.
7 VDD power_in Power supply pin with 18 V turn-on and 7.5 V turn-off thresholds, startup current below 30 mA and operating current below 10 mA.
8 OPWM output Totem-pole output driving the external PWM power MOSFET, with a clamped gate output voltage of 17.5 V.
9 GND power_in Power ground and signal ground reference; all voltages on the other pins are specified with respect to this pin.
10 DET input Auxiliary-winding sense input for PWM over-power offset, valley detection and output over-voltage protection, which latches the controller when the flat voltage exceeds 2.5 V during output OVP.
11 FB input Feedback input carrying the output voltage level, with a 5 kΩ equivalent input impedance and a 1/3 attenuator to the CSPWM/FB comparator, activating open-loop or overload protection if above about 4.2 V for more than 50 ms.
12 RT bidirectional Adjustable over-temperature protection and external latch trigger; a constant current flows out of this pin, and latch mode is activated when the RT voltage drops below 0.8 V typical until the AC plug is removed.
13 VIN power_in Line-voltage sense input through a voltage divider that sets the RANGE pin state and provides brown-in/out under-voltage protection with a 1.00 V typical threshold.
14 ZCD input Zero-current detection input from the PFC inductor auxiliary winding that starts a new PFC cycle; pulling it below 0.2 V typical disables PFC switching, and the pin is rated to 12.0 V maximum.
15 NC unconnected No connection.
16 HV power_in High-voltage startup pin connected to the AC line through a resistor (100 kΩ typical) to supply high charging current to the VDD capacitor, rated to 500 V.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-16
Category Power Management (PMIC)
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Turn-On Threshold Voltage VDD-ON 16.5 18 19.5 V 7
PWM Off Threshold Voltage VDD-PWM-OFF 9 10 11 V 7
Turn-Off Threshold Voltage VDD-OFF 6.5 7.5 8.5 V 7
Startup Current IDD-ST 20 30 µA VDD = VDD−ON − 0.16 V, Gate Open 7
Operating Current IDD-OP 10 mA VDD = 15 V, OPFC, OPWM = 100 kHz, CL−PFC, CL−PWM = 2 nF 7
Operating Current at PWM-Off Phase IDD-PWM-OFF 70 120 170 µA VDD = VDD−PWM−OFF − 0.5 V 7
VDD Over-Voltage Protection (Latch-Off) VDD-OVP 26.5 27.5 28.5 V 7
Supply Current Drawn from HV Pin IHV 1.3 mA VAC = 90 V (VDC = 120 V), VDD = 0 V 7
Threshold Voltage for AC Input Under-Voltage Protection VVIN-UVP 0.95 1 1.05 V 7
High VVIN Threshold for RANGE Comparator VVIN-RANGE-H 2.4 2.45 2.5 V 7
Low VVIN Threshold for RANGE Comparator VVIN-RANGE-L 2.05 2.1 2.15 V 7
Output Low Voltage of RANGE Pin VRANGE-OL 0.5 V IO = 1 mA 7
PFC Maximum On Time tON-MAX-PFC 22 25 28 µs 7
Feedback Comparator Reference Voltage VREF 2.465 2.5 2.535 V 7
Clamp High Feedback Voltage VINV-H 2.7 2.75 2.8 V RANGE = Open 7
Clamp High Feedback Voltage VINV-H 2.6 2.65 2.7 V RANGE = Ground 7
Clamp Low Feedback Voltage VINV-L 2.25 2.35 2.45 V 8
PWM and PFC Off Threshold for Brownout Protection VINV-BO 1.15 1.2 1.25 V 8
Limited Voltage on COMP Pin for Brownout Protection VCOMP-BO 1.55 1.6 1.65 V 8
Comparator Output High Voltage VCOMP 4.8 6 V 8
Zero Duty Cycle Voltage on COMP Pin VOZ 1.1 1.25 1.4 V 8
PFC Gate Output Clamping Voltage VZ 14 15.5 17 V VDD = 25 V 8
PFC Gate Output Voltage Low VOL 1.5 V VDD = 15 V, IO = 100 mA 8
PFC Gate Output Voltage High VOH 8 V VDD = 15 V, IO = 100 mA 8
Propagation Delay (PFC) tPD 110 200 ns 8
Open-Loop Protection Threshold Voltage VFB-OLP 3.9 4.2 4.5 V 9
The Debounce Time for Open Loop Protection tFB-OLP 40 50 60 ms 9
Zero Duty-cycle Input Voltage VOZ 0.7 0.9 1.1 V 9
Maximum On Time (PWM) tON-MAX-PWM 38 45 52 µs 9
Minimum Off Time tOFF-MIN 7 8 9 µs VFB ≥ VN, TA = 25°C 9
Beginning of Green-On Mode at FB Voltage Level VN 1.95 2.1 2.25 V 9
Beginning of Green-Off Mode at FB Voltage Level VG 1 1.15 1.3 V 9
Start Timer (Time-Out Timer) tSTARTER-PWM 1.85 2.25 2.65 ms VFB < VG 10
PWM Gate Output Clamping Voltage VCLAMP 16 17.5 19 V VDD = 25 V 10
PWM Gate Output Voltage High VOH 8 V VDD = 15 V, IO = 100 mA 10
The Limit Voltage on CSPWM Pin for Over Power Compensation VLIMIT 0.81 0.84 0.87 V IDET < 75 µA, TA = 25°C 10
CSPWM Pin Floating Clamped High Voltage VCS-FLOATING 4.5 5 V CSPWM Pin Floating 10
Internal Threshold Temperature for OTP TOTP 125 140 155 °C 10
Internal Source Current of RT Pin IRT 90 100 110 µA 10
Latch-Mode Triggering Voltage VRT-LATCH 0.75 0.8 0.85 V 10
Debounce Time for Externally Triggering tRT-OTP-L 70 110 150 µs VRT < VRT−OTP−LEVEL 10
Comparator Reference Voltage (DET PIN OVP) VDET-OVP 2.45 2.5 2.55 V 9
Delay Time from Valley Signal Detected to Output Turn-on tVALLEY-DELAY 150 200 250 ns 9
Power Dissipation PD 800 mW 6
DC Supply Voltage VDD 30 V 6
HV VHV 500 V 6
OPFC, OPWM VH -0.3 25 V 6
Others (INV, COMP, CSPFC, DET, FB, CSPWM, RT) VL -0.3 7 V 6
Input Voltage to ZCD Pin VZCD -0.3 12 V 6
Thermal Resistance (Junction-to-Air) JA 104 °C/W 6
Thermal Resistance (Junction-to-Case) JC 41 °C/W 6
Operating Junction Temperature TJ -40 150 °C 6
Storage Temperature Range TSTG -55 150 °C 6
Lead Temperature (Soldering) TL 260 °C Soldering 10 Seconds 6
ESD Human Body Model ESD 4500 V All Pins Except HV Pin, JESD22-A114 6
ESD Charged Device Model ESD 1250 V All Pins Except HV Pin, JESD22-C101 6
Operating Ambient Temperature TA -40 105 °C 6
Continuously Operating Voltage VOP 25 V 6
Minimum Startup Voltage on HV Pin VHV-MIN 50 V 6

CAD (KiCad official)

  • Symbol: FAN6921BMRMY
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: fan6921bmrmy-etched.step / fan6921bmrmy-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); fan6921bmrmy.step / fan6921bmrmy.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (21 pp, sha256 c25ecf9cbe9ba0c2, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF