component

FAN3181TMX

Public Made by Adom

by adom

onsemi Gate Drive ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icsfan3181tmxfactory-2.0.0extractor-text

Verified FAN3181TMX

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: FAN3181TMX · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 21-page datasheet
  • ✓distributor: lcsc C903475, digikey FAN3181TMXCT-ND, mouser 512-FAN3181TMX
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-jd8h58gj/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ fan3181tmx.kicad_sym✓ fan3181tmx.kicad_mod✓ fan3181tmx.step
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Ray Publish 0.1.0 51e7d80 8d ago

FAN3181TMX

onsemi · Gate Drive ICs · SOIC-8

FAN3181TMX from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN input Input signal controls the output, the output is in-phase (non-inverting) with this input, and IN has a 100 k pull-down resistor.
2 FO/SD output Open-drain fault output and shutdown pin that signals the main controller when the driver has detected a fault and deactivated the output.
3 VCC power_in Power supply input whose bypass capacitor to GND must be placed as close as possible to the VCC pin; fixed supply voltage is 25 V max (recommended) and absolute maximum is 30.0 V.
4 GND power_in Ground reference that should connect to the IGBT emitter or shunt resistor with a short trace.
5 CIN input Analog input for over-current detection.
6 GS output Provides active Miller clamping of the IGBT gate during the off period to prevent parasitic turn-on from high collector-to-emitter dv/dt, with the clamp closing when the gate falls below about 1.5 V (typical).
7 OUT output Gate driver output, typically 1.5 A sourcing and 2.0 A sinking at VCC = 15 V.
8 DESAT input Input for detecting IGBT desaturation; a fault is flagged when the DESAT voltage exceeds the typical 6.4 V threshold.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-8
Category Power Management ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Fixed Supply Voltage VCC UVLO 25 V 5
Input Voltage VIN 0 V Max printed as VCC 5
Operating Ambient Temperature Range TA -40 125 °C 5
Fixed Supply Voltage VCC -0.3 30 V 5
Output 1 Voltage VOUT -0.3 V Max printed as VCC+0.3 5
Output 2 Voltage VGS -0.3 V Max printed as VCC+0.3 5
IN, FO/SD, DESAT, VCIN, and VFO Voltage VIN -0.3 V Max printed as VCC+0.3 5
Operating Junction Temperature TJ -55 150 °C 5
Storage Temperature Range TSTG -55 150 °C 5
Electrostatic Discharge Capability, Human Body Model ESDHBM 2 kV Single value printed, placed as max 5
Electrostatic Discharge Capability, Charged Device Model ESDCDM 500 V Single value printed, placed as max 5
Quiescent Current for VCC IQCC 600 850 1050 A VIN= 0 V 6
VCC Supply UV Trip Voltage VCCUV 11 12 13 V 6
VCC Supply UV Hysteresis VCCHYS 0.5 1 1.5 V 6
VCC Supply UV Filter Time tVCCUV 5 10 15 s 6
Operating Current for VCC ICC 1.5 2 mA fIN= 20 kHz 6
High Level Input Voltage for IN VIHT 1.6 2 V 6
Low Level Input Voltage for IN VILT 0.8 1.2 V 6
High Level Logic Input Bias Current IIN+ 125 150 200 A VIN= VCC 6
Logic Input Pull-Down Resistance RIN 75 100 120 k 6
Output HIGH Short-Circuit Pulse Current IO+ 1 1.5 A VO=0 V, VIN=5 V with PW=10 µs 6
Output LOW Short-Circuit Pulse Current IO- 1.5 2 A VO=15 V, VIN=0 V with PW=10 µs 6
Soft Turn-Off Sink Current ISOFT 20 30 40 mA VCIN=1 V, VO=VCC 6
Over-Current Detect Threshold VCINTH 450 500 550 mV 6
Short-Circuit Input Current ICIN 5 10 15 µA VCIN=1 V 6
Desaturation Threshold Voltage VDESAT 6 6.4 6.8 V 6
Current Source IDESAT 215 250 285 µA IN=HIGH 6
Switch On Resistance RONSAT 2.5 5 6
GS Pin Threshold Voltage VGSTH 1.2 1.5 1.8 V 6
GS Pin Low Level Clamp Voltage VCLAMP 110 250 mV IGS=50 mA 6
GS Pin Clamp Current IGSCLAMP 0.5 1 A VGS=GND + 2.5 V 6
Clamp Switch Resistance RONCLAMP 2.2 4.5 6
FO/SD High Threshold Voltage VFOSDH 1.6 2 V 6
FO/SD Low Threshold Voltage VFOSDL 0.8 1.2 V 6
Fault Output On Resistance RDSFO 250 400 IFO=5 mA 6
Turn-On Propagation Delay tON 10 15 20 ns VIN From 0 V to 5 V 7
Turn-Off Propagation Delay tOFF 12 17 22 ns VIN From 5 V to 0 V 7
Turn-On Rise Time tR 15 20 ns 7
Turn-Off Fall Time tF 10 17 ns 7
Fault Output Duration tFAULT 75 110 145 µs 7
Desat Blanking Time tDESABLK 1.8 2.8 3.8 µs VDESAT = 6.5 V 7
FO/SD to Output LOW Propagation Delay tFOSD 17 22 ns 7
CIN Pin Leading-Edge Blanking Time tCINBLT 300 400 ns 7
Time from CIN Triggering to FO tCINFO 250 350 450 ns From VCIN=1 V to FO Turn-Off 7
Time from CIN Triggering to Output Turn-Off tCINOFF 330 430 530 ns From VCIN=1 V to Gate Turn-Off 7
Time from Clamp Triggering to Output Turn-Off tCLAMP 6 10 ns 7
Time from DESAT Triggering to Output Turn-Off tDESAT 330 430 530 ns 7
Input Logic Hysteresis VINHYST 0.4 V 6
High Level Output Voltage (VCC- VOUT) VOH 0.8 V IOUT=100 mA 6
Low Level Output Voltage VOL 0.35 V IOUT=100 mA 6
Low Level Logic Input Bias Current IIN- 1 A VIN= 0 V 6
Fault Output Leakage Current IFOSDLK 1 µA VFOSD=VCC 6
Fault Output Low Level Voltage VFOL 0.1 V VMCU=5 V, RPULLUP=20 k 6
Propagation Delay Mismatching MT 12 ns /tON-tOFF/ 7
Minimum Input Pulse Width Response at the Output tONMIN 40 ns 7
Thermal Resistance Junction-Air θJA 200 °C/W JEDEC JESD51-2, JESD51-3; 8-SOP 5
Power Dissipation PD 0.625 W JEDEC JESD51-2, JESD51-3; 8-SOP 5

CAD (KiCad official)

  • Symbol: FAN3181TMX
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: fan3181tmx-etched.step / fan3181tmx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); fan3181tmx.step / fan3181tmx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (21 pp, sha256 8cbc16fd3b9f2f3c, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF