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FAD7191M1X

Public Made by Adom

by adom

onsemi Gate Drive ICs, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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FAD7191M1X

onsemi · Gate Drive ICs · SOP-14

FAD7191M1X from onsemi, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 HIN input Logic input for high-side gate driver output, 3.3 V/5 V compatible, referenced to VSS with logic 1 threshold min 2.5 V and logic 0 max 1.2 V.
2 LIN input Logic input for low-side gate driver output, 3.3 V/5 V compatible, referenced to VSS with logic 1 threshold min 2.5 V and logic 0 max 1.2 V.
3 VSS power_in Logic ground for the 14-SOP, reference for VB, VDD and logic inputs.
4 EN input Enable input with internal pull-up, range -0.3 V to VDD + 0.3 V.
5 COM power_in Power ground for the 14-SOP and low-side driver return, rated VDD - 25 V to VDD + 0.3 V absolute maximum.
6 LO output Low-side driver output, 4.5 A source/sink capability, swinging between COM and VDD.
7 VDD power_in Low-side and logic power supply voltage, recommended 10 V to 22 V (absolute maximum 25 V).
8 NC unconnected No connect.
9 NC unconnected No connect.
10 NC unconnected No connect.
11 VS power_in High-side floating supply return, recommended offset up to 600 V and operates down to -9.8 V typical for VBS = 15 V.
12 HO output High-side driver output, 4.5 A source/sink capability, swinging between VS and VB.
13 VB power_in High-side floating supply, recommended VS + 10 V to VS + 22 V (absolute maximum 625 V).
14 NC unconnected No connect.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOP-14
Category Power Management ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High-side floating supply voltage (abs max) VB -0.3 625 V TA = -40°C to 125°C 5
Low-side and logic supply voltage (abs max) VDD -0.3 25 V 5
Allowable offset voltage slew rate dVS/dt 50 V/ns 5
Power dissipation 14-SOP PD 0.8 W TA = 25°C 5
Junction temperature TJ 150 °C 5
Storage temperature TS -55 150 °C 5
ESD Human Body Model 14-SOP ESD 2000 V JESD22-A114 5
ESD Charged Device Model ESD 2000 V JESD22-C101 5
Thermal resistance junction-to-ambient 14-SOP θJA 156 °C/W 76.2 × 114.3 × 1.6 mm FR-4 PCB 5
High-side floating supply offset voltage VS 600 V 5
Low-side and logic supply voltage VDD 10 22 V 5
Ambient temperature TA -40 125 °C 5
VDD and VBS UV positive-going threshold VDDUV+/VBSUV+ 7.8 8.8 9.8 V 6
VDD and VBS UV negative-going threshold VDDUV-/VBSUV- 7.2 8.3 9.1 V 6
VDD UVLO hysteresis VDDHYS 0.5 V 6
Offset supply leakage current ILK 50 μA VB = VS = 600 V 6
Quiescent VBS supply current IQBS 45 110 μA VIN = 0 V or 5 V 6
Quiescent VDD supply current IQDD 75 150 μA VIN = 0 V or 5 V 6
Operating VBS supply current IPBS 400 800 μA fIN = 20 kHz, RMS value 6
Operating VDD supply current IPDD 400 800 μA fIN = 20 kHz, RMS value 6
Logic 1 input voltage VIH 2.5 V 6
Logic 0 input voltage VIL 1.2 V 6
Logic 1 input bias current (HIN/LIN) IIN+ 25 50 μA VIN = 5 V 6
Logic 0 input bias current (HIN/LIN) IIN- 1 2 μA VIN = 0 V 6
Enable high input bias current IEN+ -100 -50 -10 μA EN = 5 V 6
Enable low input bias current IEN- -140 -75 -20 μA EN = 0 V 6
Input pull-down resistance RIN 100 200 kΩ 6
High-level output voltage, VBIAS-VO VOH 1.35 V No Load 6
Low-level output voltage VOL 35 mV No Load 6
Output HIGH short-circuit pulsed current IO+ 3.5 4.5 A VO = 0 V, VIN = 5 V with PW < 10μs 6
Output LOW short-circuit pulsed current IO- 3.5 4.5 A VO = 15 V, VIN = 0 V with PW < 10 μs 6
Allowable negative VS pin voltage for HIN propagation to HO VS -9.8 -9 V VBS = 15V 6
Allowable COM-VSS ground offset COM-VSS -7 V 14-SOP, VDD = 15 V, VSS = 0 V 6
Turn-on propagation delay ton 140 200 ns VS = 0 V 7
Turn-off propagation delay toff 140 200 ns VS = 0 V 7
Delay matching MT 55 ns 7
Turn-on rise time tr 25 50 ns 7
Turn-off fall time tf 25 50 ns 7

CAD (KiCad official)

  • Symbol: FAD7191M1X
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: fad7191m1x-etched.step / fad7191m1x-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); fad7191m1x.step / fad7191m1x.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (14 pp, sha256 384a42b965485373, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF