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Initial commit: component/f35sqa001g-wwt

Ray ·20222f555f ·4d ago
2 files changed +204
README.mdadded+45
@@ -0,0 +1,45 @@+# F35SQA001G-WWT++**FORESEE** · NAND FLASH · WSON-8-EP(6x8)++F35SQA001G-WWT from FORESEE, in a WSON-8-EP(6x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CS# | input | Chip Select enables the device when low and deselects it when high (DO/SIO pins high-Z, standby power); CS# must go high to low after power-up before a new instruction is accepted and must track VCC during ramp up/down. |+| 2 | DO/SIO1 | bidirectional | Serial Data Output in standard SPI (data shifted out on the falling edge of CLK) and bidirectional SIO1 in Dual and Quad SPI. |+| 3 | WP#/SIO2 | bidirectional | Write Protect prevents the Status Register from being written (with BP[3:0], TB, BPRWD, SP) and becomes SIO2 in Quad SPI; with QE=1 it has no WP# function. |+| 4 | GND | power_in | Ground. |+| 5 | DI/SIO0 | bidirectional | Serial Data Input in standard SPI (latched on the rising edge of CLK) and bidirectional SIO0 in Dual and Quad SPI. |+| 6 | CLK | input | Serial Clock input provides timing for serial input and output operations, up to 104 MHz. |+| 7 | HOLD#/SIO3 | bidirectional | Active-low Hold pauses the device while CS# is low in standard and Dual SPI (DO high-Z, DI and CLK ignored) and becomes SIO3 during Quad SPI operations. |+| 8 | VCC | power_in | Power supply, 2.7V to 3.6V. |+| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | FORESEE |+| Package | WSON-8-EP(6x8) |+| Category | Memory |+| Pins | 9 |++## CAD (KiCad official)++- Symbol: `F35SQA001G-WWT`+- Footprint: `Package_SON:WSON-8-1EP_8x6mm_P1.27mm_EP3.4x4.3mm`+- 3D model: WSON-8-EP(6x8), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.75 mm nominal WSON height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)+- 3D model files: `f35sqa001g-wwt-etched.step` / `f35sqa001g-wwt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `f35sqa001g-wwt.step` / `f35sqa001g-wwt.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [FORESEE datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589835465445568513) (43 pp, sha256 `d4f0b78fd1dde2d2`, retrieved 2026-10-01, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/f35sqa001g-wwt-datasheet.pdf)
page.jsonadded+159
@@ -0,0 +1,159 @@+{+  "slug": "f35sqa001g-wwt",+  "version": "0.1.0",+  "type": "component",+  "description": "FORESEE NAND FLASH, WSON-8-EP(6x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "memory",+    "f35sqa001g-wwt",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "f35sqa001g-wwt.kicad_sym",+    "f35sqa001g-wwt.kicad_mod",+    "f35sqa001g-wwt.glb",+    "f35sqa001g-wwt.step",+    "f35sqa001g-wwt.lbr",+    "docs/hero.png",+    "docs/f35sqa001g-wwt-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "component": {+    "mpn": "F35SQA001G-WWT",+    "manufacturer": "FORESEE",+    "package": "WSON-8-EP(6x8)",+    "pin_count": 9,+    "category": "Memory",+    "subcategory": "NAND FLASH",+    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589835465445568513",+    "parts": {+      "symbol": "f35sqa001g-wwt.kicad_sym",+      "footprint": "f35sqa001g-wwt.kicad_mod",+      "model_3d": "f35sqa001g-wwt-etched.glb",+      "model_3d_plain": "f35sqa001g-wwt.glb",+      "model_3d_step": "f35sqa001g-wwt-etched.step",+      "model_3d_step_plain": "f35sqa001g-wwt.step",+      "lbr": "f35sqa001g-wwt.lbr"+    },+    "distributor_links": {+      "lcsc": "C5126827"+    },+    "distributor_check": {+      "checked_at": "2026-10-01T17:08:16Z",+      "source": "Component Ocean /api/assign-pns",+      "digikey": {+        "pn": null,+        "status": "no match"+      },+      "mouser": {+        "pn": null,+        "status": "no match"+      }+    },+    "pins": [+      {+        "number": "1",+        "name": "CS#",+        "type": "input",+        "description": "Chip Select enables the device when low and deselects it when high (DO/SIO pins high-Z, standby power); CS# must go high to low after power-up before a new instruction is accepted and must track VCC during ramp up/down."+      },+      {+        "number": "2",+        "name": "DO/SIO1",+        "type": "bidirectional",+        "description": "Serial Data Output in standard SPI (data shifted out on the falling edge of CLK) and bidirectional SIO1 in Dual and Quad SPI."+      },+      {+        "number": "3",+        "name": "WP#/SIO2",+        "type": "bidirectional",+        "description": "Write Protect prevents the Status Register from being written (with BP[3:0], TB, BPRWD, SP) and becomes SIO2 in Quad SPI; with QE=1 it has no WP# function."+      },+      {+        "number": "4",+        "name": "GND",+        "type": "power_in",+        "description": "Ground."+      },+      {+        "number": "5",+        "name": "DI/SIO0",+        "type": "bidirectional",+        "description": "Serial Data Input in standard SPI (latched on the rising edge of CLK) and bidirectional SIO0 in Dual and Quad SPI."+      },+      {+        "number": "6",+        "name": "CLK",+        "type": "input",+        "description": "Serial Clock input provides timing for serial input and output operations, up to 104 MHz."+      },+      {+        "number": "7",+        "name": "HOLD#/SIO3",+        "type": "bidirectional",+        "description": "Active-low Hold pauses the device while CS# is low in standard and Dual SPI (DO high-Z, DI and CLK ignored) and becomes SIO3 during Quad SPI operations."+      },+      {+        "number": "8",+        "name": "VCC",+        "type": "power_in",+        "description": "Power supply, 2.7V to 3.6V."+      },+      {+        "number": "9",+        "name": "EP",+        "type": "passive",+        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.2",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.2",+        "primary_model": "claude-haiku-4-5-20251001",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-5-5",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [],+        "pages_sent": 43,+        "cost_usd": 0.644,+        "at": "2026-10-01T17:07:56"+      },+      "datasheet": {+        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589835465445568513",+        "pages": 43,+        "sha256": "d4f0b78fd1dde2d2",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 9,+        "described": 9,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file