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F280049PZQR

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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F280049PZQR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

F280049PZQR from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO28 bidirectional General-purpose I/O 28 on the 3.3 V VDDIO domain; alternate functions include SCIA_RX, EPWM7_A and ERRORSTS.
2 XRSn bidirectional Device reset input and watchdog reset output, open-drain with internal pull-up; a 2.2 kΩ to 10 kΩ resistor to VDDIO is required and any capacitor to VSS must be 100 nF or less.
3 VDDIO power_in 3.3 V digital I/O supply; place at least a 0.1 µF decoupling capacitor on each VDDIO pin.
4 VDD power_in 1.2 V digital logic supply; use at least 20 µF total decoupling near the VDD pins when the internal regulator is not used.
5 VSS power_in Digital ground; all VSS pins must be connected to board ground.
6 A6,PGA5_OF input ADC-A input 6; the same pin also provides the optional PGA-5 output filter node and a CMPSS-5 comparator input.
7 B2,C6,PGA3_OF input ADC-B input 2 (shared with ADC-C input 6 and the optional PGA-3 output filter node).
8 B3,VDAC input ADC-B input 3, also the optional external reference for the on-chip DAC; an internal 100 pF capacitor to VSSA is present and at least 1 µF is required if used as DAC reference.
9 A2,B6,PGA1_OF input ADC-A input 2 (shared with ADC-B input 6 and the optional PGA-1 output filter node).
10 A3 input ADC-A input 3, also routed to CMPSS-1 comparator inputs and AIO233.
11 VDDA power_in 3.3 V analog supply; place a decoupling capacitor of at least 2.2 µF to VSSA on each VDDA pin.
12 VSSA power_in Analog ground for the ADC, PGA, DAC and comparator circuits.
13 PGA5_GND power_in PGA-5 Kelvin ground reference; ideally equal to VSSA.
14 PGA1_GND power_in PGA-1 Kelvin ground reference for PGA1_IN; ideally equal to VSSA.
15 PGA3_GND power_in PGA-3 Kelvin ground reference for PGA3_IN; ideally equal to VSSA.
16 PGA5_IN input PGA-5 non-inverting input; the amplified signal (gain 3, 6, 12 or 24) feeds the ADC and CMPSS.
17 C4 input ADC-C input 4, also routed to CMPSS-5 comparator inputs and AIO239.
18 PGA1_IN input PGA-1 input with programmable gain of 3, 6, 12 or 24; also CMPSS-1 high comparator input 2.
19 C0 input ADC-C input 0, also routed to CMPSS-1 comparator inputs and AIO237.
20 PGA3_IN input PGA-3 input with programmable gain of 3, 6, 12 or 24.
21 C2 input ADC-C input 2, also routed to CMPSS-3 comparator inputs and AIO244.
22 A1,DACB_OUT input ADC-A input 1; this pin is also the buffered 12-bit DAC-B output (DACB_OUT).
23 A0,B15,C15,DACA_OUT input ADC-A input 0 (also ADC-B input 15 and ADC-C input 15); this pin is also the buffered 12-bit DAC-A output (DACA_OUT).
24 VREFHIB,VREFHIC bidirectional ADC-B and ADC-C high reference; drive externally in external-reference mode, device-driven in internal-reference mode, and place at least 2.2 µF between this pin and the matching VREFLO pin.
25 VREFHIA bidirectional ADC-A high reference; drive externally in external-reference mode or device-driven in internal mode, with at least 2.2 µF between VREFHIA and VREFLOA and no external loading.
26 VREFLOB,VREFLOC input ADC-B and ADC-C low reference, to be tied to analog ground.
27 VREFLOA input ADC-A low reference, to be tied to analog ground.
28 C5,PGA6_IN input ADC-C input 5 (shared with the PGA-6 input and CMPSS-6 comparator input).
29 C1 input ADC-C input 1, also routed to CMPSS-2 comparator inputs and AIO238.
30 PGA2_IN input PGA-2 input with programmable gain of 3, 6, 12 or 24.
31 C3,PGA4_IN input ADC-C input 3 (shared with the PGA-4 input), also routed to CMPSS-4 comparator inputs and AIO245.
32 PGA2_GND,PGA4_GND,PGA6_GND power_in Common Kelvin ground reference for PGA-2, PGA-4 and PGA-6; ideally equal to VSSA.
33 VSSA power_in Analog ground.
34 VDDA power_in 3.3 V analog supply; decouple each pin with at least 2.2 µF to VSSA.
35 A5 input ADC-A input 5, also routed to CMPSS-2 comparator inputs and AIO234.
36 A4,B8,PGA2_OF input ADC-A input 4 (shared with ADC-B input 8 and the optional PGA-2 output filter node).
37 A8,PGA6_OF input ADC-A input 8 (shared with the optional PGA-6 output filter node).
38 A9 input ADC-A input 9, also routed to CMPSS-6 comparator inputs and AIO236.
39 B4,C8,PGA4_OF input ADC-B input 4 (shared with ADC-C input 8 and the optional PGA-4 output filter node).
40 A10,B1,C10,PGA7_OF input ADC-A input 10 (shared with ADC-B input 1, ADC-C input 10 and the optional PGA-7 output filter node).
41 B0 input ADC-B input 0, also routed to CMPSS-7 comparator inputs and AIO241.
42 PGA7_GND power_in PGA-7 Kelvin ground reference; ideally equal to VSSA.
43 PGA7_IN input PGA-7 input with programmable gain of 3, 6, 12 or 24; also CMPSS-7 comparator input.
44 C14 input ADC-C input 14, also routed to CMPSS-7 comparator inputs and AIO246.
45 VSS power_in Digital ground.
46 VDD power_in 1.2 V digital logic supply; decouple per the VDD decoupling rules.
47 VDDIO power_in 3.3 V digital I/O supply; decouple each pin with at least 0.1 µF.
48 FLT2 unconnected Flash test pin 2 reserved for TI; must remain unconnected (or tied to VSS through 4.7 kΩ or greater).
49 FLT1 unconnected Flash test pin 1 reserved for TI; must remain unconnected (or tied to VSS through 4.7 kΩ or greater).
50 GPIO13 bidirectional General-purpose I/O 13; alternate functions include EPWM7_B, CANB_RX, EQEP1_INDEX, SCIB_RX, PMBUSA_ALERT and FSIRXA_CLK.
51 GPIO12 bidirectional General-purpose I/O 12; alternate functions include EPWM7_A, CANB_TX, EQEP1_STROBE, SCIB_TX, PMBUSA_CTL and FSIRXA_D0.
52 GPIO11 bidirectional General-purpose I/O 11; alternate functions include EPWM6_B, SCIB_RX, OUTPUTXBAR7, EQEP1_B, SPIA_STE and FSIRXA_D1.
53 GPIO33 bidirectional General-purpose I/O 33; alternate functions include I2CA_SCL (open-drain), SPIB_STE, LINA_RX, SD1_C3, FSIRXA_CLK and CANA_RX.
54 GPIO16 bidirectional General-purpose I/O 16; alternate functions include SPIA_SIMO, CANB_TX, EPWM5_A, SCIA_TX, SD1_D1 and XCLKOUT.
55 GPIO17 bidirectional General-purpose I/O 17; alternate functions include SPIA_SOMI, CANB_RX, EPWM5_B, SCIA_RX, SD1_C1 and PMBUSA_SDA.
56 GPIO24 bidirectional General-purpose I/O 24; alternate functions include OUTPUTXBAR1, EQEP2_A, EPWM8_A, SPIB_SIMO, SD1_D1 and ERRORSTS (active-low output).
57 GPIO25 bidirectional General-purpose I/O 25; alternate functions include OUTPUTXBAR2, EQEP2_B, SPIB_SOMI, SD1_C1, FSITXA_D1 and SCIA_RX.
58 GPIO26 bidirectional General-purpose I/O 26; alternate functions include OUTPUTXBAR3, EQEP2_INDEX, SPIB_CLK, SD1_D2, FSITXA_D0 and I2CA_SDA.
59 GPIO27 bidirectional General-purpose I/O 27; alternate functions include OUTPUTXBAR4, EQEP2_STROBE, SPIB_STE, SD1_C2, FSITXA_CLK and I2CA_SCL.
60 TCK input JTAG test clock with internal pull-up enabled.
61 GPIO37/TDO output JTAG test data output (default function); tri-stated when JTAG is inactive, so an internal or external pull-up is needed to avoid a floating GPIO input.
62 TMS bidirectional JTAG test mode select with internal pull-up, clocked on TCK rising edge; a 2.2 kΩ external pull-up to VDDIO is recommended, and the device has no TRSTn pin.
63 GPIO35/TDI input JTAG test data input (default function); internal pull-up is disabled by default, so enable it or add an external pull-up to avoid a floating input.
64 GPIO32 bidirectional General-purpose I/O 32; alternate functions include I2CA_SDA, SPIB_CLK, EPWM8_B, LINA_TX, SD1_D3, FSIRXA_D0 and CANA_TX.
65 GPIO56 bidirectional General-purpose I/O 56; alternate functions include SPIA_CLK, EQEP2_STROBE, SCIB_TX, SD1_D3, SPIB_SIMO and EQEP1_A.
66 GPIO57 bidirectional General-purpose I/O 57; alternate functions include SPIA_STE, EQEP2_INDEX, SCIB_RX, SD1_C3, SPIB_SOMI and EQEP1_B.
67 GPIO58 bidirectional General-purpose I/O 58; alternate functions include OUTPUTXBAR1, SPIB_CLK, SD1_D4, LINA_TX, CANB_TX and EQEP1_STROBE.
68 GPIO18_X2 bidirectional General-purpose I/O 18 shared with crystal output X2; GPIO18 and its mux options are usable only when the system is clocked from INTOSC and X1 has an external pull-down (about 1 kΩ recommended).
69 X1 bidirectional Crystal oscillator input or single-ended 3.3 V clock input; software must configure this pin before enabling the crystal oscillator.
70 VDDIO power_in 3.3 V digital I/O supply; decouple each pin with at least 0.1 µF.
71 VDD power_in 1.2 V digital logic supply; decouple per the VDD decoupling rules.
72 VSS power_in Digital ground.
73 VREGENZ input Internal regulator enable with internal pull-down; tie to VSS to enable the internal VREG and to VDDIO to use an external VDD supply.
74 GPIO8 bidirectional General-purpose I/O 8; alternate functions include EPWM5_A, CANB_TX, ADCSOCAO, EQEP1_STROBE, SCIA_TX, SPIA_SIMO, I2CA_SCL and FSITXA_D1.
75 GPIO4 bidirectional General-purpose I/O 4; alternate functions include EPWM3_A, OUTPUTXBAR3, CANA_TX and FSIRXA_CLK.
76 GPIO3 bidirectional General-purpose I/O 3; alternate functions include EPWM2_B, OUTPUTXBAR2, PMBUSA_SCL, SPIA_CLK, SCIA_RX and FSIRXA_D0.
77 GPIO2 bidirectional General-purpose I/O 2; alternate functions include EPWM2_A, OUTPUTXBAR1, PMBUSA_SDA, SCIA_TX and FSIRXA_D1.
78 GPIO1 bidirectional General-purpose I/O 1; alternate functions include EPWM1_B and I2CA_SCL (open-drain).
79 GPIO0 bidirectional General-purpose I/O 0; alternate functions include EPWM1_A and I2CA_SDA (open-drain).
80 VDDIO_SW power_in 3.3 V supply for the internal DC/DC regulator; must always be connected to VDDIO and needs 20 µF input capacitance when the DC/DC is used.
81 GPIO23_VSW bidirectional GPIO23 that by default serves as the DC/DC switch output VSW when DCDCEN is set; it has about 100 pF internal capacitance and is not suited to fast switching.
82 VSS_SW power_in Internal DC/DC regulator ground; must always be connected to VSS.
83 GPIO22_VFBSW bidirectional GPIO22 that by default serves as the DC/DC feedback VFBSW; when the internal DC/DC is used, route it to the node where L(VSW) meets the VDD rail close to the device.
84 GPIO7 bidirectional General-purpose I/O 7; alternate functions include EPWM4_B, OUTPUTXBAR5, EQEP1_B, CANB_RX, SPIB_SIMO and FSITXA_CLK.
85 GPIO40 bidirectional General-purpose I/O 40; alternate functions include PMBUSA_SDA, FSIRXA_D0, SCIB_TX and EQEP1_A.
86 VSS power_in Digital ground.
87 VDD power_in 1.2 V digital logic supply.
88 VDDIO power_in 3.3 V digital I/O supply; decouple each pin with at least 0.1 µF.
89 GPIO5 bidirectional General-purpose I/O 5; alternate functions include EPWM3_B, OUTPUTXBAR3, CANA_RX, SPIA_STE and FSITXA_D1.
90 GPIO9 bidirectional General-purpose I/O 9; alternate functions include EPWM5_B, SCIB_TX, OUTPUTXBAR6, EQEP1_INDEX, SCIA_RX, SPIA_CLK and FSITXA_D0.
91 GPIO39 bidirectional General-purpose I/O 39; alternate functions include CANB_RX and FSIRXA_CLK.
92 GPIO59 bidirectional General-purpose I/O 59; alternate functions include OUTPUTXBAR2, SPIB_STE, SD1_C4, LINA_RX, CANB_RX and EQEP1_INDEX.
93 GPIO10 bidirectional General-purpose I/O 10; alternate functions include EPWM6_A, CANB_RX, ADCSOCBO, EQEP1_A, SCIB_TX, SPIA_SOMI, I2CA_SDA and FSITXA_CLK.
94 GPIO34 bidirectional General-purpose I/O 34; alternate functions include OUTPUTXBAR1 and PMBUSA_SDA (open-drain).
95 GPIO15 bidirectional General-purpose I/O 15; alternate functions include EPWM8_B, SCIB_RX, OUTPUTXBAR4, PMBUSA_SCL, SPIB_STE and EQEP2_B.
96 GPIO14 bidirectional General-purpose I/O 14; alternate functions include EPWM8_A, SCIB_TX, OUTPUTXBAR3, PMBUSA_SDA, SPIB_CLK and EQEP2_A.
97 GPIO6 bidirectional General-purpose I/O 6; alternate functions include EPWM4_A, OUTPUTXBAR4, SYNCOUT, EQEP1_A, CANB_TX, SPIB_SOMI and FSITXA_D0.
98 GPIO30 bidirectional General-purpose I/O 30; alternate functions include CANA_RX, SPIB_SIMO, OUTPUTXBAR7, EQEP1_STROBE and SD1_D4.
99 GPIO31 bidirectional General-purpose I/O 31; alternate functions include CANA_TX, SPIB_SOMI, OUTPUTXBAR8, EQEP1_INDEX, SD1_C4 and FSIRXA_D1.
100 GPIO29 bidirectional General-purpose I/O 29; alternate functions include SCIA_TX, EPWM7_B, OUTPUTXBAR6, EQEP1_B, SD1_C3, EQEP2_INDEX, LINA_RX, SPIB_STE and ERRORSTS.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: F280049PZQR
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: f280049pzqr-etched.step / f280049pzqr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); f280049pzqr.step / f280049pzqr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (277 pp, sha256 867e7bb5ada6819c, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF