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F280049CPZS

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Contents

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F280049CPZS

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

F280049CPZS from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO28 bidirectional General-purpose digital I/O 28; multiplexed function pin per Figure 5-1 pinout diagram.
2 XRSn bidirectional External reset, active-low; bidirectional open-drain pin that resets the device when driven low externally and is driven low by the device during internal resets.
3 VDDIO power_in Digital I/O supply voltage rail.
4 VDD power_in Digital core logic supply voltage rail (1.2V nominal).
5 VSS power_in Digital ground.
6 A6,PGA5_OF passive ADC-A channel 6 analog input pin, multiplexed with the PGA5 output-filter node.
7 B2,C6,PGA3_OF passive ADC-B channel 2 / ADC-C channel 6 analog input pin, multiplexed with the PGA3 output-filter node.
8 B3,VDAC passive ADC-B channel 3 analog input pin, multiplexed with the buffered DAC voltage reference (VDAC) pin.
9 A2,B6,PGA1_OF passive ADC-A channel 2 / ADC-B channel 6 analog input pin, multiplexed with the PGA1 output-filter node.
10 A3 input ADC-A channel 3 analog input.
11 VDDA power_in Analog supply voltage for ADC/analog blocks.
12 VSSA power_in Analog ground.
13 PGA5_GND passive Ground reference pin for programmable gain amplifier PGA5.
14 PGA1_GND passive Ground reference pin for programmable gain amplifier PGA1.
15 PGA3_GND passive Ground reference pin for programmable gain amplifier PGA3.
16 PGA5_IN input PGA5 analog input.
17 C4 input ADC-C channel 4 analog input.
18 PGA1_IN input PGA1 analog input.
19 C0 input ADC-C channel 0 analog input.
20 PGA3_IN input PGA3 analog input.
21 C2 input ADC-C channel 2 analog input.
22 A1,DACB_OUT passive ADC-A channel 1 analog input pin, multiplexed with the buffered DAC-B analog output.
23 A0,B15,C15,DACA_OUT passive ADC-A channel 0 / ADC-B channel 15 / ADC-C channel 15 analog input pin, multiplexed with the buffered DAC-A analog output.
24 VREFHIB,VREFHIC passive High reference voltage input shared by ADC-B and ADC-C.
25 VREFHIA passive High reference voltage input for ADC-A.
26 VREFLOB,VREFLOC passive Low reference voltage input shared by ADC-B and ADC-C.
27 VREFLOA passive Low reference voltage input for ADC-A.
28 C5,PGA6_IN input ADC-C channel 5 analog input pin, multiplexed with the PGA6 analog input.
29 C1 input ADC-C channel 1 analog input.
30 PGA2_IN input PGA2 analog input.
31 C3,PGA4_IN input ADC-C channel 3 analog input pin, multiplexed with the PGA4 analog input.
32 PGA2_GND,PGA4_GND,PGA6_GND passive Shared ground reference pin for programmable gain amplifiers PGA2, PGA4, and PGA6.
33 VSSA power_in Analog ground.
34 VDDA power_in Analog supply voltage for ADC/analog blocks.
35 A5 input ADC-A channel 5 analog input.
36 A4,B8,PGA2_OF passive ADC-A channel 4 / ADC-B channel 8 analog input pin, multiplexed with the PGA2 output-filter node.
37 A8,PGA6_OF passive ADC-A channel 8 analog input pin, multiplexed with the PGA6 output-filter node.
38 A9 input ADC-A channel 9 analog input.
39 B4,C8,PGA4_OF passive ADC-B channel 4 / ADC-C channel 8 analog input pin, multiplexed with the PGA4 output-filter node.
40 A10,B1,C10,PGA7_OF passive ADC-A channel 10 / ADC-B channel 1 / ADC-C channel 10 analog input pin, multiplexed with the PGA7 output-filter node.
41 B0 input ADC-B channel 0 analog input.
42 PGA7_GND passive Ground reference pin for programmable gain amplifier PGA7.
43 PGA7_IN input PGA7 analog input.
44 C14 input ADC-C channel 14 analog input.
45 VSS power_in Digital ground.
46 VDD power_in Digital core logic supply voltage rail.
47 VDDIO power_in Digital I/O supply voltage rail.
48 FLT2 input Dedicated fault-related pin (function label only; detailed operation not given on the pinout diagram).
49 FLT1 input Dedicated fault-related pin (function label only; detailed operation not given on the pinout diagram).
50 GPIO13 bidirectional General-purpose digital I/O 13; multiplexed function pin per Figure 5-1 pinout diagram.
51 GPIO12 bidirectional General-purpose digital I/O 12; multiplexed function pin per Figure 5-1 pinout diagram.
52 GPIO11 bidirectional General-purpose digital I/O 11; multiplexed function pin per Figure 5-1 pinout diagram.
53 GPIO33 bidirectional General-purpose digital I/O 33; multiplexed function pin per Figure 5-1 pinout diagram.
54 GPIO16 bidirectional General-purpose digital I/O 16; multiplexed function pin per Figure 5-1 pinout diagram.
55 GPIO17 bidirectional General-purpose digital I/O 17; multiplexed function pin per Figure 5-1 pinout diagram.
56 GPIO24 bidirectional General-purpose digital I/O 24; multiplexed function pin per Figure 5-1 pinout diagram.
57 GPIO25 bidirectional General-purpose digital I/O 25; multiplexed function pin per Figure 5-1 pinout diagram.
58 GPIO26 bidirectional General-purpose digital I/O 26; multiplexed function pin per Figure 5-1 pinout diagram.
59 GPIO27 bidirectional General-purpose digital I/O 27; multiplexed function pin per Figure 5-1 pinout diagram.
60 TCK input JTAG test clock input.
61 GPIO37/TDO bidirectional General-purpose digital I/O 37, multiplexed with JTAG TDO output.
62 TMS input JTAG test-mode select input.
63 GPIO35/TDI bidirectional General-purpose digital I/O 35, multiplexed with JTAG TDI input.
64 GPIO32 bidirectional General-purpose digital I/O 32; multiplexed function pin per Figure 5-1 pinout diagram.
65 GPIO56 bidirectional General-purpose digital I/O 56; multiplexed function pin per Figure 5-1 pinout diagram.
66 GPIO57 bidirectional General-purpose digital I/O 57; multiplexed function pin per Figure 5-1 pinout diagram.
67 GPIO58 bidirectional General-purpose digital I/O 58; multiplexed function pin per Figure 5-1 pinout diagram.
68 GPIO18_X2 bidirectional General-purpose digital I/O 18, multiplexed with the external crystal oscillator X2 pin.
69 X1 passive Crystal oscillator input pin for the on-chip crystal oscillator.
70 VDDIO power_in Digital I/O supply voltage rail.
71 VDD power_in Digital core logic supply voltage rail.
72 VSS power_in Digital ground.
73 VREGENZ input Internal voltage regulator enable/disable control input (VREG enable, active low per naming).
74 GPIO8 bidirectional General-purpose digital I/O 8; multiplexed function pin per Figure 5-1 pinout diagram.
75 GPIO4 bidirectional General-purpose digital I/O 4; multiplexed function pin per Figure 5-1 pinout diagram.
76 GPIO3 bidirectional General-purpose digital I/O 3; multiplexed function pin per Figure 5-1 pinout diagram.
77 GPIO2 bidirectional General-purpose digital I/O 2; multiplexed function pin per Figure 5-1 pinout diagram.
78 GPIO1 bidirectional General-purpose digital I/O 1; multiplexed function pin per Figure 5-1 pinout diagram.
79 GPIO0 bidirectional General-purpose digital I/O 0; multiplexed function pin per Figure 5-1 pinout diagram.
80 VDDIO_SW power_in Switched digital I/O supply voltage rail (associated with internal switching regulator function).
81 GPIO23_VSW bidirectional General-purpose digital I/O 23, multiplexed with the switching-regulator VSW node function.
82 VSS_SW power_in Switched digital ground rail (associated with internal switching regulator function).
83 GPIO22_VFBSW bidirectional General-purpose digital I/O 22, multiplexed with the switching-regulator VFBSW feedback function.
84 GPIO7 bidirectional General-purpose digital I/O 7; multiplexed function pin per Figure 5-1 pinout diagram.
85 GPIO40 bidirectional General-purpose digital I/O 40; multiplexed function pin per Figure 5-1 pinout diagram.
86 VSS power_in Digital ground.
87 VDD power_in Digital core logic supply voltage rail.
88 VDDIO power_in Digital I/O supply voltage rail.
89 GPIO5 bidirectional General-purpose digital I/O 5; multiplexed function pin per Figure 5-1 pinout diagram.
90 GPIO9 bidirectional General-purpose digital I/O 9; multiplexed function pin per Figure 5-1 pinout diagram.
91 GPIO39 bidirectional General-purpose digital I/O 39; multiplexed function pin per Figure 5-1 pinout diagram.
92 GPIO59 bidirectional General-purpose digital I/O 59; multiplexed function pin per Figure 5-1 pinout diagram.
93 GPIO10 bidirectional General-purpose digital I/O 10; multiplexed function pin per Figure 5-1 pinout diagram.
94 GPIO34 bidirectional General-purpose digital I/O 34; multiplexed function pin per Figure 5-1 pinout diagram.
95 GPIO15 bidirectional General-purpose digital I/O 15; multiplexed function pin per Figure 5-1 pinout diagram.
96 GPIO14 bidirectional General-purpose digital I/O 14; multiplexed function pin per Figure 5-1 pinout diagram.
97 GPIO6 bidirectional General-purpose digital I/O 6; multiplexed function pin per Figure 5-1 pinout diagram.
98 GPIO30 bidirectional General-purpose digital I/O 30; multiplexed function pin per Figure 5-1 pinout diagram.
99 GPIO31 bidirectional General-purpose digital I/O 31; multiplexed function pin per Figure 5-1 pinout diagram.
100 GPIO29 bidirectional General-purpose digital I/O 29; multiplexed function pin per Figure 5-1 pinout diagram.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: F280049CPZS
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: f280049cpzs-etched.step / f280049cpzs-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); f280049cpzs.step / f280049cpzs.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (277 pp, sha256 867e7bb5ada6819c, retrieved 2026-09-24, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-sonnet-5 (text+vision), consensus claude-opus-4-8 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF