component
F280049CPZQR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownF280049CPZQR
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)
F280049CPZQR from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GPIO28 | bidirectional | General Purpose Input/Output 28; multiplexable to SCIA_RX, EPWM7_A, or other control functions. |
| 2 | XRSn | bidirectional | Device reset input and watchdog reset output with open-drain output buffer and internal pull-up resistor. |
| 3 | VDDIO | power_in | 3.3V digital I/O power supply pin; requires 0.1µF decoupling capacitor. |
| 4 | VDD | power_in | 1.2V digital logic power supply pin; requires minimum 20µF total decoupling capacitance. |
| 5 | VSS | power_in | Digital ground pin. |
| 6 | A6/PGA5_OF | passive | ADC-A input 6 or PGA-5 output filter; analog input with passive multiplexing to programmable gain amplifier output. |
| 7 | B2/C6/PGA3_OF | passive | ADC-B input 2, ADC-C input 6, or PGA-3 output filter; analog multiplexed input or programmable gain amplifier output. |
| 8 | B3/VDAC | passive | ADC-B input 3 or external reference voltage for on-chip DAC; 100pF capacitor to VSSA is required internally. |
| 9 | A2/B6/PGA1_OF | passive | ADC-A input 2, ADC-B input 6, or PGA-1 output filter; multiplexed analog input or programmable gain amplifier output. |
| 10 | A3 | input | ADC-A input 3; single-ended analog input for analog-to-digital converter A. |
| 11 | VDDA | power_in | 3.3V analog power supply pin; requires minimum 2.2µF decoupling capacitor to VSSA. |
| 12 | VSSA | power_in | Analog ground pin. |
| 13 | PGA5_GND | passive | PGA-5 ground reference pin for Kelvin sensing of programmable gain amplifier ground. |
| 14 | PGA1_GND | passive | PGA-1 ground reference pin for Kelvin sensing of programmable gain amplifier ground. |
| 15 | PGA3_GND | passive | PGA-3 ground reference pin for Kelvin sensing of programmable gain amplifier ground. |
| 16 | PGA5_IN | input | PGA-5 input pin for programmable gain amplifier with gains of 3, 6, 12, or 24. |
| 17 | C4 | input | ADC-C input 4; single-ended analog input for analog-to-digital converter C. |
| 18 | PGA1_IN | input | PGA-1 input pin for programmable gain amplifier with gains of 3, 6, 12, or 24. |
| 19 | C0 | input | ADC-C input 0; single-ended analog input for analog-to-digital converter C. |
| 20 | PGA3_IN | input | PGA-3 input pin for programmable gain amplifier with gains of 3, 6, 12, or 24. |
| 21 | C2 | input | ADC-C input 2; single-ended analog input for analog-to-digital converter C. |
| 22 | A1/DACB_OUT | passive | ADC-A input 1 or buffered DAC-B output; multiplexed analog input or 12-bit digital-to-analog converter output. |
| 23 | A0/B15/C15/DACA_OUT | passive | ADC-A input 0, ADC-B input 15, ADC-C input 15, or buffered DAC-A output; multiplexed analog input or 12-bit DAC output. |
| 24 | VREFHIB/VREFHIC | bidirectional | ADC-B and ADC-C high reference voltage; internally driven in internal reference mode or externally driven in external reference mode; requires 2.2µF capacitor. |
| 25 | VREFHIA | bidirectional | ADC-A high reference voltage; internally driven in internal reference mode or externally driven in external reference mode; requires 2.2µF capacitor. |
| 26 | VREFLOB/VREFLOC | input | ADC-B and ADC-C low reference voltage pins; typically connected to VSSA. |
| 27 | VREFLOA | input | ADC-A low reference voltage pin; typically connected to VSSA. |
| 28 | C5/PGA6_IN | passive | ADC-C input 5 or PGA-6 input; multiplexed analog input or programmable gain amplifier input. |
| 29 | C1 | input | ADC-C input 1; single-ended analog input for analog-to-digital converter C. |
| 30 | PGA2_IN | input | PGA-2 input pin for programmable gain amplifier with gains of 3, 6, 12, or 24. |
| 31 | C3/PGA4_IN | passive | ADC-C input 3 or PGA-4 input; multiplexed analog input or programmable gain amplifier input. |
| 32 | PGA2_GND/PGA4_GND/PGA6_GND | passive | Ground reference pins for PGA-2, PGA-4, and PGA-6 Kelvin sensing. |
| 33 | VSSA | power_in | Analog ground pin. |
| 34 | VDDA | power_in | 3.3V analog power supply pin; requires minimum 2.2µF decoupling capacitor to VSSA. |
| 35 | A5 | input | ADC-A input 5; single-ended analog input for analog-to-digital converter A. |
| 36 | A4/B8/PGA2_OF | passive | ADC-A input 4, ADC-B input 8, or PGA-2 output filter; multiplexed analog input or programmable gain amplifier output. |
| 37 | A8/PGA6_OF | passive | ADC-A input 8 or PGA-6 output filter; analog input or programmable gain amplifier output. |
| 38 | A9 | input | ADC-A input 9; single-ended analog input for analog-to-digital converter A. |
| 39 | B4/C8/PGA4_OF | passive | ADC-B input 4, ADC-C input 8, or PGA-4 output filter; multiplexed analog input or programmable gain amplifier output. |
| 40 | A10/B1/C10/PGA7_OF | passive | ADC-A input 10, ADC-B input 1, ADC-C input 10, or PGA-7 output filter; multiplexed analog input or programmable gain amplifier output. |
| 41 | B0 | input | ADC-B input 0; single-ended analog input for analog-to-digital converter B. |
| 42 | PGA7_GND | passive | PGA-7 ground reference pin for Kelvin sensing of programmable gain amplifier ground. |
| 43 | PGA7_IN | input | PGA-7 input pin for programmable gain amplifier with gains of 3, 6, 12, or 24. |
| 44 | C14 | input | ADC-C input 14; single-ended analog input for analog-to-digital converter C. |
| 45 | VSS | power_in | Digital ground pin. |
| 46 | VDD | power_in | 1.2V digital logic power supply pin; requires minimum 20µF total decoupling capacitance. |
| 47 | VDDIO | power_in | 3.3V digital I/O power supply pin; requires 0.1µF decoupling capacitor. |
| 48 | FLT2 | unconnected | Flash test pin 2 reserved for TI; must be left unconnected. |
| 49 | FLT1 | unconnected | Flash test pin 1 reserved for TI; must be left unconnected. |
| 50 | GPIO13 | bidirectional | General Purpose Input/Output 13; multiplexable to various control signals. |
| 51 | GPIO12 | bidirectional | General Purpose Input/Output 12; multiplexable to various control signals. |
| 52 | GPIO11 | bidirectional | General Purpose Input/Output 11; multiplexable to various control signals. |
| 53 | GPIO33 | bidirectional | General Purpose Input/Output 33; multiplexable to I2C-A, SPIB, and CAN-A signals. |
| 54 | GPIO16 | bidirectional | General Purpose Input/Output 16; multiplexable to SPI, ePWM, and CAN signals. |
| 55 | GPIO17 | bidirectional | General Purpose Input/Output 17; multiplexable to SPI, ePWM, and other signals. |
| 56 | GPIO24 | bidirectional | General Purpose Input/Output 24; multiplexable to ePWM, SPI, and PMBus signals. |
| 57 | GPIO25 | bidirectional | General Purpose Input/Output 25; multiplexable to output X-BAR and SPI signals. |
| 58 | GPIO26 | bidirectional | General Purpose Input/Output 26; multiplexable to output X-BAR and SDFM signals. |
| 59 | GPIO27 | bidirectional | General Purpose Input/Output 27; multiplexable to output X-BAR and SDFM signals. |
| 60 | TCK | input | JTAG test clock input with internal pull-up resistor for boundary scan interface. |
| 61 | GPIO37/TDO | output | General Purpose Input/Output 37 or JTAG test data output; open-drain output during JTAG activity, high-impedance otherwise. |
| 62 | TMS | bidirectional | JTAG test mode select input with internal pull-up resistor; sampled on TCK rising edge. |
| 63 | GPIO35/TDI | input | General Purpose Input/Output 35 or JTAG test data input; enable internal or external pull-up to avoid floating input. |
| 64 | GPIO32 | bidirectional | General Purpose Input/Output 32; multiplexable to I2C-A, SPI, and LIN signals. |
| 65 | GPIO56 | bidirectional | General Purpose Input/Output 56; multiplexable to SPI and SDFM signals. |
| 66 | GPIO57 | bidirectional | General Purpose Input/Output 57; multiplexable to SPI and eQEP signals. |
| 67 | GPIO58 | bidirectional | General Purpose Input/Output 58; multiplexable to output X-BAR and SDFM signals. |
| 68 | GPIO18_X2 | bidirectional | General Purpose Input/Output 18 or crystal oscillator output; usable as GPIO only when X1 has external pull-down and INTOSC provides system clock. |
| 69 | X1 | bidirectional | Crystal oscillator input or single-ended clock input; requires software configuration before enabling oscillator. |
| 70 | VDDIO | power_in | 3.3V digital I/O power supply pin; requires 0.1µF decoupling capacitor. |
| 71 | VDD | power_in | 1.2V digital logic power supply pin; requires minimum 20µF total decoupling capacitance. |
| 72 | VSS | power_in | Digital ground pin. |
| 73 | VREGENZ | input | Internal regulator enable with internal pull-down resistor; connect low to enable internal VREG, high for external power. |
| 74 | GPIO8 | bidirectional | General Purpose Input/Output 8; multiplexable to ePWM, CAN, and other control signals. |
| 75 | GPIO4 | bidirectional | General Purpose Input/Output 4; multiplexable to ePWM, CAN, and other control signals. |
| 76 | GPIO3 | bidirectional | General Purpose Input/Output 3; multiplexable to ePWM, PMBus, and other control signals. |
| 77 | GPIO2 | bidirectional | General Purpose Input/Output 2; multiplexable to ePWM, output X-BAR, and PMBus signals. |
| 78 | GPIO1 | bidirectional | General Purpose Input/Output 1; multiplexable to ePWM-1 output B and I2C-A signals. |
| 79 | GPIO0 | bidirectional | General Purpose Input/Output 0; multiplexable to ePWM-1 output A and I2C-A SDA. |
| 80 | VDDIO_SW | power_in | 3.3V power supply for internal DC/DC regulator input; requires 20µF large bulk capacitor. |
| 81 | GPIO23_VSW | bidirectional | General Purpose Input/Output 23 or internal DC/DC regulator switch output; ~100pF internal capacitance. |
| 82 | VSS_SW | power_in | Internal DC/DC regulator ground; must be connected to VSS pin. |
| 83 | GPIO22_VFBSW | bidirectional | General Purpose Input/Output 22 or internal DC/DC regulator feedback signal; connect to VSW node when using DC/DC. |
| 84 | GPIO7 | bidirectional | General Purpose Input/Output 7; multiplexable to ePWM-4 output B and other control signals. |
| 85 | GPIO40 | bidirectional | General Purpose Input/Output 40; multiplexable to PMBus and FSI signals. |
| 86 | VSS | power_in | Digital ground pin. |
| 87 | VDD | power_in | 1.2V digital logic power supply pin; requires minimum 20µF total decoupling capacitance. |
| 88 | VDDIO | power_in | 3.3V digital I/O power supply pin; requires 0.1µF decoupling capacitor. |
| 89 | GPIO5 | bidirectional | General Purpose Input/Output 5; multiplexable to ePWM-3 output B and CAN signals. |
| 90 | GPIO9 | bidirectional | General Purpose Input/Output 9; multiplexable to ePWM-5 output B and SCI signals. |
| 91 | GPIO39 | bidirectional | General Purpose Input/Output 39; multiplexable to CAN-B and FSI signals. |
| 92 | GPIO59 | bidirectional | General Purpose Input/Output 59; multiplexable to output X-BAR and SDFM signals. |
| 93 | GPIO10 | bidirectional | General Purpose Input/Output 10; multiplexable to ePWM-6 output A and ADC signals. |
| 94 | GPIO34 | bidirectional | General Purpose Input/Output 34; multiplexable to output X-BAR and PMBus signals. |
| 95 | GPIO15 | bidirectional | General Purpose Input/Output 15; multiplexable to ePWM-8 output B and output X-BAR signals. |
| 96 | GPIO14 | bidirectional | General Purpose Input/Output 14; multiplexable to ePWM-8 output A and output X-BAR signals. |
| 97 | GPIO6 | bidirectional | General Purpose Input/Output 6; multiplexable to ePWM-4 output A and various control signals. |
| 98 | GPIO30 | bidirectional | General Purpose Input/Output 30; multiplexable to CAN-A and output X-BAR signals. |
| 99 | GPIO31 | bidirectional | General Purpose Input/Output 31; multiplexable to CAN-A and output X-BAR signals. |
| 100 | GPIO29 | bidirectional | General Purpose Input/Output 29; multiplexable to SCI-A and SDFM signals. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-100(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 100 |
CAD (KiCad official)
- Symbol:
F280049CPZQR - Footprint:
Package_QFP:LQFP-100_14x14mm_P0.5mm - 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files:
f280049cpzqr-etched.step/f280049cpzqr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);f280049cpzqr.step/f280049cpzqr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (277 pp, sha256
867e7bb5ada6819c, retrieved 2026-10-06, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).