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F280041PZQR

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Texas Instruments Microcontrollers (MCU/MPU/SOC), QFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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F280041PZQR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · QFP-100(14x14)

F280041PZQR from Texas Instruments, in a QFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO28 bidirectional General-purpose I/O 28 with default GPIO function and alternates SCIA_RX, EPWM7_A, OUTPUTXBAR5, EQEP1_A, SD1_D3, EQEP2_STROBE, LINA_TX, SPIB_CLK and ERRORSTS (active-low error status output).
2 XRSn bidirectional Device reset input and watchdog reset output on an open-drain output with internal pull-up; a 2.2 kΩ to 10 kΩ resistor should be connected between XRSn and VDDIO, and any noise-filter capacitor to VSS must be 100 nF or less.
3 VDDIO power_in 3.3 V digital I/O supply pin; place a decoupling capacitor of at least 0.1 µF on each VDDIO pin.
4 VDD power_in 1.2 V digital logic supply pin; TI recommends a total VDD decoupling capacitance of about 20 µF minimum near the VDD pins when the internal regulator is used.
5 VSS power_in Digital ground pin that must be connected to the board ground.
6 A6/PGA5_OF input ADC-A analog input 6, also the PGA-5 output filter pin PGA5_OF and digital input AIO228 on the ADC pin.
7 B2/C6/PGA3_OF input ADC-B analog input 2, also ADC-C input 6, PGA-3 output filter PGA3_OF and digital input AIO226.
8 B3/VDAC input ADC-B analog input 3; the VDAC pin is an optional external reference for the on-chip DACs with a 100 pF capacitor to VSSA that cannot be disabled, and at least 1 µF must be added if it is used as the DAC reference.
9 A2/B6/PGA1_OF input ADC-A analog input 2, also ADC-B input 6, PGA-1 output filter PGA1_OF and digital input AIO224.
10 A3 input ADC-A analog input 3, also CMPSS-1 comparator inputs and digital input AIO233.
11 VDDA power_in 3.3 V analog supply pin; place a decoupling capacitor of at least 2.2 µF connected to VSSA on each VDDA pin.
12 VSSA power_in Analog ground for the ADC, PGA, DAC and comparator subsystem.
13 PGA5_GND power_in PGA-5 ground Kelvin reference for PGA5_IN, ideally equal to VSSA.
14 PGA1_GND power_in PGA-1 ground Kelvin reference for PGA1_IN, ideally equal to VSSA, and the PGA tolerates a small VSSA offset.
15 PGA3_GND power_in PGA-3 ground Kelvin reference for PGA3_IN, ideally equal to VSSA.
16 PGA5_IN input PGA-5 amplifier input, amplified with selectable gains of 3, 6, 12 or 24.
17 C4 input ADC-C analog input 4, also CMPSS-5 comparator inputs and digital input AIO239.
18 PGA1_IN input PGA-1 amplifier input, amplified with selectable gains of 3, 6, 12 or 24, also CMPSS-1 high comparator input 2.
19 C0 input ADC-C analog input 0, also CMPSS-1 comparator inputs and digital input AIO237.
20 PGA3_IN input PGA-3 amplifier input, amplified with selectable gains of 3, 6, 12 or 24.
21 C2 input ADC-C analog input 2, also CMPSS-3 comparator inputs and digital input AIO244.
22 A1/DACB_OUT input ADC-A analog input 1, which is multiplexed with the buffered DAC-B output DACB_OUT and digital input AIO232.
23 A0/B15/C15/DACA_OUT input ADC-A analog input 0, also ADC-B input 15, ADC-C input 15, buffered DAC-A output DACA_OUT and digital input AIO231.
24 VREFHIB, VREFHIC bidirectional ADC-B and ADC-C high reference; in external reference mode it is driven externally, in internal reference mode the device drives it, at least 2.2 µF must sit between this pin and its VREFLO pin, and it must not be loaded externally.
25 VREFHIA bidirectional ADC-A high reference; in external reference mode it is driven externally, in internal reference mode the device drives it, at least 2.2 µF must sit between VREFHIA and VREFLOA, and it must not be loaded externally.
26 VREFLOB, VREFLOC input ADC-B and ADC-C low reference voltage input.
27 VREFLOA input ADC-A low reference voltage input.
28 C5/PGA6_IN input ADC-C analog input 5, shared with the PGA-6 amplifier input PGA6_IN, and also CMPSS-6 comparator inputs and digital input AIO240.
29 C1 input ADC-C analog input 1, also CMPSS-2 comparator inputs and digital input AIO238.
30 PGA2_IN input PGA-2 amplifier input, amplified with selectable gains of 3, 6, 12 or 24.
31 C3/PGA4_IN input ADC-C analog input 3, shared with the PGA-4 amplifier input PGA4_IN, and also CMPSS-4 comparator inputs and digital input AIO245.
32 PGA2_GND, PGA4_GND, PGA6_GND power_in Shared PGA ground Kelvin references for PGA-2, PGA-4 and PGA-6, ideally equal to VSSA.
33 VSSA power_in Analog ground pin that must be connected to the board analog ground.
34 VDDA power_in 3.3 V analog supply pin; place a decoupling capacitor of at least 2.2 µF connected to VSSA.
35 A5 input ADC-A analog input 5, also CMPSS-2 comparator inputs and digital input AIO234.
36 A4/B8/PGA2_OF input ADC-A analog input 4, also ADC-B input 8, PGA-2 output filter PGA2_OF, CMPSS-2 comparator inputs and digital input AIO225.
37 A8/PGA6_OF input ADC-A analog input 8, also PGA-6 output filter PGA6_OF and digital input AIO229.
38 A9 input ADC-A analog input 9, also CMPSS-6 comparator inputs and digital input AIO236.
39 B4/C8/PGA4_OF input ADC-B analog input 4, also ADC-C input 8, PGA-4 output filter PGA4_OF and digital input AIO227.
40 A10/B1/C10/PGA7_OF input ADC-A analog input 10, also ADC-B input 1, ADC-C input 10, PGA-7 output filter PGA7_OF and digital input AIO230.
41 B0 input ADC-B analog input 0, also CMPSS-7 comparator inputs and digital input AIO241.
42 PGA7_GND power_in PGA-7 ground Kelvin reference for PGA7_IN, ideally equal to VSSA.
43 PGA7_IN input PGA-7 amplifier input, amplified with selectable gains of 3, 6, 12 or 24.
44 C14 input ADC-C analog input 14, also CMPSS-7 comparator inputs and digital input AIO246.
45 VSS power_in Digital ground pin that must be connected to the board ground.
46 VDD power_in 1.2 V digital logic supply pin; decoupling capacitors are required on each VDD pin as specified for the internal or external VREG mode.
47 VDDIO power_in 3.3 V digital I/O supply pin; place a decoupling capacitor of at least 0.1 µF on each VDDIO pin.
48 FLT2 unconnected Flash test pin 2 is reserved for TI and must remain unconnected.
49 FLT1 unconnected Flash test pin 1 is reserved for TI and must remain unconnected.
50 GPIO13 bidirectional General-purpose I/O 13 with alternates EPWM7_B, CANB_RX, EQEP1_INDEX, SCIB_RX, PMBUSA_ALERT (open-drain) and FSIRXA_CLK.
51 GPIO12 bidirectional General-purpose I/O 12 with alternates EPWM7_A, CANB_TX, EQEP1_STROBE, SCIB_TX, PMBUSA_CTL and FSIRXA_D0.
52 GPIO11 bidirectional General-purpose I/O 11 with alternates EPWM6_B, SCIB_RX, OUTPUTXBAR7, EQEP1_B, SPIA_STE and FSIRXA_D1.
53 GPIO33 bidirectional General-purpose I/O 33 with alternates I2CA_SCL (open-drain), SPIB_STE, OUTPUTXBAR4, LINA_RX, SD1_C3, FSIRXA_CLK and CANA_RX.
54 GPIO16 bidirectional General-purpose I/O 16 with alternates SPIA_SIMO, CANB_TX, OUTPUTXBAR7, EPWM5_A, SCIA_TX, SD1_D1, EQEP1_STROBE, PMBUSA_SCL and XCLKOUT.
55 GPIO17 bidirectional General-purpose I/O 17 with alternates SPIA_SOMI, CANB_RX, OUTPUTXBAR8, EPWM5_B, SCIA_RX, SD1_C1, EQEP1_INDEX and PMBUSA_SDA.
56 GPIO24 bidirectional General-purpose I/O 24 with alternates OUTPUTXBAR1, EQEP2_A, EPWM8_A, SPIB_SIMO, SD1_D1, PMBUSA_SCL, SCIA_TX and ERRORSTS (active-low error status output).
57 GPIO25 bidirectional General-purpose I/O 25 with alternates OUTPUTXBAR2, EQEP2_B, SPIB_SOMI, SD1_C1, FSITXA_D1, PMBUSA_SDA and SCIA_RX.
58 GPIO26 bidirectional General-purpose I/O 26 with alternates OUTPUTXBAR3, EQEP2_INDEX, SPIB_CLK, SD1_D2, FSITXA_D0, PMBUSA_CTL and I2CA_SDA (open-drain).
59 GPIO27 bidirectional General-purpose I/O 27 with alternates OUTPUTXBAR4, EQEP2_STROBE, SPIB_STE, SD1_C2, FSITXA_CLK, PMBUSA_ALERT and I2CA_SCL (open-drain).
60 TCK input JTAG test clock input with an internal pull-up resistor.
61 GPIO37/TDO output JTAG test data output by default, tri-stated when no JTAG activity so the pin must be biased by an internal or external pull-up to avoid floating GPIO input; alternates GPIO37, OUTPUTXBAR2, I2CA_SCL, SCIA_TX, CANA_TX, LINA_TX, EQEP1_B and PMBUSA_ALERT.
62 TMS bidirectional JTAG test mode select with an internal pull-up; an external pull-up of about 2.2 kΩ to VDDIO is recommended to keep JTAG in reset during normal operation.
63 GPIO35/TDI input JTAG test data input by default with internal pull-up disabled, so an internal or external pull-up must be enabled when used as TDI to avoid a floating input; alternates GPIO35, SCIA_RX, I2CA_SDA, CANA_RX, PMBUSA_SCL, LINA_RX, EQEP1_A and PMBUSA_CTL.
64 GPIO32 bidirectional General-purpose I/O 32 with alternates I2CA_SDA (open-drain), SPIB_CLK, EPWM8_B, LINA_TX, SD1_D3, FSIRXA_D0 and CANA_TX.
65 GPIO56 bidirectional General-purpose I/O 56 with alternates SPIA_CLK, EQEP2_STROBE, SCIB_TX, SD1_D3, SPIB_SIMO and EQEP1_A.
66 GPIO57 bidirectional General-purpose I/O 57 with alternates SPIA_STE, EQEP2_INDEX, SCIB_RX, SD1_C3, SPIB_SOMI and EQEP1_B.
67 GPIO58 bidirectional General-purpose I/O 58 with alternates OUTPUTXBAR1, SPIB_CLK, SD1_D4, LINA_TX, CANB_TX and EQEP1_STROBE.
68 GPIO18_X2 bidirectional General-purpose I/O 18 that doubles as the X2 crystal oscillator output; the GPIO18 function is usable only when the system is clocked from INTOSC and X1 has an external pull-down (recommended 1 kΩ).
69 X1 bidirectional Crystal oscillator input or single-ended 3.3 V clock input that must be configured by initialization software before the oscillator is enabled; GPIO19 is internally tied to X1 and must be held as input with pull-up disabled.
70 VDDIO power_in 3.3 V digital I/O supply pin; place a decoupling capacitor of at least 0.1 µF on each VDDIO pin.
71 VDD power_in 1.2 V digital logic supply pin; decoupling capacitors are required on each VDD pin as specified for the internal or external VREG mode.
72 VSS power_in Digital ground pin that must be connected to the board ground.
73 VREGENZ input Internal regulator enable with internal pull-down: connect to VSS to enable the internal VREG, or to VDDIO to use an external VDD supply.
74 GPIO8 bidirectional General-purpose I/O 8 with alternates EPWM5_A, CANB_TX, ADCSOCAO, EQEP1_STROBE, SCIA_TX, SPIA_SIMO, I2CA_SCL (open-drain) and FSITXA_D1.
75 GPIO4 bidirectional General-purpose I/O 4 with alternates EPWM3_A, OUTPUTXBAR3, CANA_TX and FSIRXA_CLK.
76 GPIO3 bidirectional General-purpose I/O 3 with alternates EPWM2_B, OUTPUTXBAR2, PMBUSA_SCL (open-drain), SPIA_CLK, SCIA_RX and FSIRXA_D0.
77 GPIO2 bidirectional General-purpose I/O 2 with alternates EPWM2_A, OUTPUTXBAR1, PMBUSA_SDA (open-drain), SCIA_TX and FSIRXA_D1.
78 GPIO1 bidirectional General-purpose I/O 1 with alternates EPWM1_B and I2CA_SCL (open-drain).
79 GPIO0 bidirectional General-purpose I/O 0 with alternates EPWM1_A and I2CA_SDA (open-drain).
80 VDDIO_SW power_in 3.3 V supply for the internal DC/DC regulator that must be tied to VDDIO and needs about 20 µF bulk input capacitance when the DC/DC is used.
81 GPIO23_VSW bidirectional GPIO23 by default is the DC/DC switch output VSW when DCDCEN = 1; it can be used as GPIO23 only when the internal DC/DC is not used, and its ~100 pF internal capacitance makes it unsuitable for fast-switching signals.
82 VSS_SW power_in Internal DC/DC regulator ground that must be connected to VSS.
83 GPIO22_VFBSW bidirectional GPIO22 by default is the DC/DC feedback input VFBSW, which must be routed to the node where the inductor VSW connects to the VDD rail; it can be used as GPIO22 only when the internal DC/DC is disabled.
84 GPIO7 bidirectional General-purpose I/O 7 with alternates EPWM4_B, OUTPUTXBAR5, EQEP1_B, CANB_RX, SPIB_SIMO and FSITXA_CLK.
85 GPIO40 bidirectional General-purpose I/O 40 with alternates PMBUSA_SDA (open-drain), FSIRXA_D0, SCIB_TX and EQEP1_A.
86 VSS power_in Digital ground pin that must be connected to the board ground.
87 VDD power_in 1.2 V digital logic supply pin; decoupling capacitors are required on each VDD pin as specified for the internal or external VREG mode.
88 VDDIO power_in 3.3 V digital I/O supply pin; place a decoupling capacitor of at least 0.1 µF on each VDDIO pin.
89 GPIO5 bidirectional General-purpose I/O 5 with alternates EPWM3_B, OUTPUTXBAR3, CANA_RX, SPIA_STE and FSITXA_D1.
90 GPIO9 bidirectional General-purpose I/O 9 with alternates EPWM5_B, SCIB_TX, OUTPUTXBAR6, EQEP1_INDEX, SCIA_RX, SPIA_CLK and FSITXA_D0.
91 GPIO39 bidirectional General-purpose I/O 39 with alternates CANB_RX and FSIRXA_CLK.
92 GPIO59 bidirectional General-purpose I/O 59 with alternates OUTPUTXBAR2, SPIB_STE, SD1_C4, LINA_RX, CANB_RX and EQEP1_INDEX.
93 GPIO10 bidirectional General-purpose I/O 10 with alternates EPWM6_A, CANB_RX, ADCSOCBO, EQEP1_A, SCIB_TX, SPIA_SOMI, I2CA_SDA (open-drain) and FSITXA_CLK.
94 GPIO34 bidirectional General-purpose I/O 34 with alternates OUTPUTXBAR1 and PMBUSA_SDA (open-drain).
95 GPIO15 bidirectional General-purpose I/O 15 with alternates EPWM8_B, SCIB_RX, OUTPUTXBAR4, PMBUSA_SCL (open-drain), SPIB_STE and EQEP2_B.
96 GPIO14 bidirectional General-purpose I/O 14 with alternates EPWM8_A, SCIB_TX, OUTPUTXBAR3, PMBUSA_SDA (open-drain), SPIB_CLK and EQEP2_A.
97 GPIO6 bidirectional General-purpose I/O 6 with alternates EPWM4_A, OUTPUTXBAR4, SYNCOUT, EQEP1_A, CANB_TX, SPIB_SOMI and FSITXA_D0.
98 GPIO30 bidirectional General-purpose I/O 30 with alternates CANA_RX, SPIB_SIMO, OUTPUTXBAR7, EQEP1_STROBE and SD1_D4.
99 GPIO31 bidirectional General-purpose I/O 31 with alternates CANA_TX, SPIB_SOMI, OUTPUTXBAR8, EQEP1_INDEX, SD1_C4 and FSIRXA_D1.
100 GPIO29 bidirectional General-purpose I/O 29 with alternates SCIA_TX, EPWM7_B, OUTPUTXBAR6, EQEP1_B, SD1_C3, EQEP2_INDEX, LINA_RX, SPIB_STE and ERRORSTS (active-low error status output).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: F280041PZQR
  • Footprint: Package_QFP:TQFP-100_14x14mm_P0.5mm
  • 3D model: QFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: f280041pzqr-etched.step / f280041pzqr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); f280041pzqr.step / f280041pzqr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (277 pp, sha256 867e7bb5ada6819c, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF