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F280041PMSR

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Texas Instruments Microcontrollers (MCU/MPU/SOC), QFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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F280041PMSR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · QFP-64(10x10)

F280041PMSR from Texas Instruments, in a QFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO29 bidirectional General-purpose I/O 29 with multiplexed functions SCIA_TX, EPWM7_B, EQEP1_B, SD1_C3, LINA_RX, SPIB_STE and ERRORSTS (active-low error status output).
2 GPIO28 bidirectional General-purpose I/O 28 with multiplexed functions SCIA_RX, EPWM7_A, EQEP1_A, SD1_D3, LINA_TX, SPIB_CLK and ERRORSTS (active-low error status output).
3 XRSn bidirectional Device reset input and watchdog reset output; open-drain with internal pull-up, with a 2.2 kΩ to 10 kΩ resistor between XRSn and VDDIO and a capacitor of 100 nF or less to VSS if used for noise filtering.
4 VDD power_in 1.2 V digital logic supply; place a minimum total decoupling capacitance of about 20 µF near the VDD pins (value depends on the internal VREG or DC-DC configuration).
5 VSS power_in Digital ground; all VSS pins must be connected to the board ground.
6 A6/PGA5_OF input ADC-A analog input 6, also the PGA-5 output filter pin PGA5_OF (optional) and digital input AIO228.
7 B2/C6/PGA3_OF input ADC-B analog input 2 and ADC-C analog input 6, also the PGA-3 output filter pin PGA3_OF (optional).
8 B3/VDAC input ADC-B analog input 3 and optional external reference for the on-chip DACs; a 100 pF capacitor to VSSA is always present, and at least 1 µF is required if used as the DAC reference.
9 A2/B6/PGA1_OF input ADC-A analog input 2 and ADC-B analog input 6, also the PGA-1 output filter pin PGA1_OF (optional).
10 PGA1_GND power_in Kelvin ground reference for PGA-1, PGA-3 and PGA-5, which should be tied to VSSA.
11 C4/PGA5_IN input ADC-C analog input 4 and PGA-5 non-inverting input PGA5_IN.
12 C0/PGA1_IN input ADC-C analog input 0 and PGA-1 input PGA1_IN.
13 C2/PGA3_IN input ADC-C analog input 2 and PGA-3 input PGA3_IN.
14 A1/DACB_OUT input ADC-A analog input 1; this pin is also the buffered DAC-B output DACB_OUT.
15 A0/B15/C15/DACA_OUT input ADC-A analog input 0 (also ADC-B 15 and ADC-C 15); this pin is also the buffered DAC-A output DACA_OUT.
16 VREFHIA bidirectional ADC high reference; driven externally in external reference mode or by the device in internal reference mode, with at least 2.2 µF placed between this pin and the matching VREFLO pin and no external loading.
17 VREFLOA input ADC low reference voltage, which should be bound to VSSA.
18 C1/PGA2_IN input ADC-C analog input 1 and PGA-2 input PGA2_IN.
19 C3/PGA4_IN input ADC-C analog input 3 and PGA-4 input PGA4_IN.
20 PGA2_GND power_in Kelvin ground reference for PGA-2, PGA-4 and PGA-6, which should be tied to VSSA.
21 VSSA power_in Analog ground for the ADC, PGA, DAC and CMPSS modules.
22 VDDA power_in 3.3 V analog supply; place at least 2.2 µF decoupling between this pin and VSSA.
23 A4/B8/PGA2_OF input ADC-A analog input 4 and ADC-B analog input 8, also the PGA-2 output filter pin PGA2_OF (optional).
24 B4/C8/PGA4_OF input ADC-B analog input 4 and ADC-C analog input 8, also the PGA-4 output filter pin PGA4_OF (optional).
25 A10/B1/C10/PGA7_OF input ADC-A analog input 10, ADC-B analog input 1 and ADC-C analog input 10, also the PGA-7 output filter pin PGA7_OF (optional).
26 VSS power_in Digital ground; must be connected to the board ground.
27 VDD power_in 1.2 V digital logic supply pin.
28 VDDIO power_in 3.3 V digital I/O supply; place at least 0.1 µF decoupling on each VDDIO pin.
29 GPIO13 bidirectional General-purpose I/O 13 with multiplexed functions EPWM7_B, CANB_RX, EQEP1_INDEX, SCIB_RX, PMBUSA_ALERT (open-drain) and FSIRXA_CLK.
30 GPIO12 bidirectional General-purpose I/O 12 with multiplexed functions EPWM7_A, CANB_TX, EQEP1_STROBE, SCIB_TX, PMBUSA_CTL and FSIRXA_D0.
31 GPIO11 bidirectional General-purpose I/O 11 with multiplexed functions EPWM6_B, SCIB_RX, OUTPUTXBAR7, EQEP1_B, SPIA_STE and FSIRXA_D1.
32 GPIO33 bidirectional General-purpose I/O 33 with multiplexed functions I2CA_SCL (open-drain), SPIB_STE, OUTPUTXBAR4, LINA_RX, SD1_C3, FSIRXA_CLK and CANA_RX.
33 GPIO16 bidirectional General-purpose I/O 16 with multiplexed functions SPIA_SIMO, CANB_TX, OUTPUTXBAR7, EPWM5_A, SCIA_TX, SD1_D1, EQEP1_STROBE, PMBUSA_SCL and XCLKOUT.
34 GPIO17 bidirectional General-purpose I/O 17 with multiplexed functions SPIA_SOMI, CANB_RX, OUTPUTXBAR8, EPWM5_B, SCIA_RX, SD1_C1, EQEP1_INDEX and PMBUSA_SDA (open-drain).
35 GPIO24 bidirectional General-purpose I/O 24 with multiplexed functions OUTPUTXBAR1, EQEP2_A, EPWM8_A, SPIB_SIMO, SD1_D1, PMBUSA_SCL, SCIA_TX and ERRORSTS (active-low error status output).
36 TCK input JTAG test clock input with an internal pull-up resistor.
37 GPIO37/TDO bidirectional JTAG test data output TDO by default, which is tri-stated when no JTAG activity is present, so an internal or external pull-up is required to avoid a floating input; alternatively GPIO37 with OUTPUTXBAR2, I2CA_SCL, SCIA_TX, CANA_TX, LINA_TX, EQEP1_B and PMBUSA_ALERT.
38 TMS bidirectional JTAG test mode select with an internal pull-up; an external 2.2 kΩ pull-up to VDDIO is recommended to keep JTAG in reset during normal operation.
39 GPIO35/TDI bidirectional JTAG test data input TDI by default, whose internal pull-up is disabled by default, so an internal pull-up must be enabled or an external pull-up added when used as TDI; alternatively GPIO35 with SCIA_RX, I2CA_SDA, CANA_RX, PMBUSA_SCL, LINA_RX and EQEP1_A.
40 GPIO32 bidirectional General-purpose I/O 32 with multiplexed functions I2CA_SDA (open-drain), SPIB_CLK, EPWM8_B, LINA_TX, SD1_D3, FSIRXA_D0 and CANA_TX.
41 GPIO18_X2 bidirectional General-purpose I/O 18 that doubles as the crystal oscillator output X2; the GPIO18 function is usable only when the system is clocked by INTOSC and X1 has an external pull-down (1 kΩ recommended).
42 X1 bidirectional Crystal oscillator input or single-ended 3.3 V clock input, which must be configured by initialization software before the crystal oscillator is enabled.
43 VDDIO power_in 3.3 V digital I/O supply; place at least 0.1 µF decoupling on each VDDIO pin.
44 VDD power_in 1.2 V digital logic supply pin.
45 VSS power_in Digital ground; must be connected to the board ground.
46 VREGENZ input Internal regulator enable with an internal pull-down; connect to VSS to enable the internal VREG or DC-DC and to VDDIO to supply VDD externally.
47 GPIO8 bidirectional General-purpose I/O 8 with multiplexed functions EPWM5_A, CANB_TX, ADCSOCAO, EQEP1_STROBE, SCIA_TX, SPIA_SIMO, I2CA_SCL (open-drain) and FSITXA_D1.
48 GPIO4 bidirectional General-purpose I/O 4 with multiplexed functions EPWM3_A, OUTPUTXBAR3, CANA_TX and FSIRXA_CLK.
49 GPIO3 bidirectional General-purpose I/O 3 with multiplexed functions EPWM2_B, OUTPUTXBAR2, PMBUSA_SCL (open-drain), SPIA_CLK, SCIA_RX and FSIRXA_D0.
50 GPIO2 bidirectional General-purpose I/O 2 with multiplexed functions EPWM2_A, OUTPUTXBAR1, PMBUSA_SDA (open-drain), SCIA_TX and FSIRXA_D1.
51 GPIO1 bidirectional General-purpose I/O 1 with multiplexed functions EPWM1_B and I2CA_SCL (open-drain).
52 GPIO0 bidirectional General-purpose I/O 0 with multiplexed functions EPWM1_A and I2CA_SDA (open-drain).
53 VDDIO_SW power_in 3.3 V supply for the internal DC-DC regulator, which must always be connected to VDDIO and needs a 20 µF bulk input capacitor when the DC-DC is used.
54 GPIO23_VSW bidirectional General-purpose I/O 23 that is the DC-DC switch output VSW when DCDCEN = 1; it has about 100 pF internal capacitance, so an alternate GPIO is recommended where fast switching response is not required.
55 VSS_SW power_in Internal DC-DC regulator ground, which must always be connected to VSS.
56 GPIO22_VFBSW bidirectional General-purpose I/O 22 that is the DC-DC feedback VFBSW when DCDCEN = 1; connect it to the node where L(VSW) connects to the VDD rail, as close to the device as possible.
57 GPIO7 bidirectional General-purpose I/O 7 with multiplexed functions EPWM4_B, OUTPUTXBAR5, EQEP1_B, CANB_RX, SPIB_SIMO and FSITXA_CLK.
58 VSS power_in Digital ground; must be connected to the board ground.
59 VDD power_in 1.2 V digital logic supply pin.
60 VDDIO power_in 3.3 V digital I/O supply; place at least 0.1 µF decoupling on each VDDIO pin.
61 GPIO5 bidirectional General-purpose I/O 5 with multiplexed functions EPWM3_B, OUTPUTXBAR3, CANA_RX, SPIA_STE and FSITXA_D1.
62 GPIO9 bidirectional General-purpose I/O 9 with multiplexed functions EPWM5_B, SCIB_TX, OUTPUTXBAR6, EQEP1_INDEX, SCIA_RX, SPIA_CLK and FSITXA_D0.
63 GPIO10 bidirectional General-purpose I/O 10 with multiplexed functions EPWM6_A, CANB_RX, ADCSOCBO, EQEP1_A, SCIB_TX, SPIA_SOMI, I2CA_SDA (open-drain) and FSITXA_CLK.
64 GPIO6 bidirectional General-purpose I/O 6 with multiplexed functions EPWM4_A, OUTPUTXBAR4, SYNCOUT, EQEP1_A, CANB_TX, SPIB_SOMI and FSITXA_D0.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

CAD (KiCad official)

  • Symbol: F280041PMSR
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: QFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: f280041pmsr-etched.step / f280041pmsr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); f280041pmsr.step / f280041pmsr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (277 pp, sha256 867e7bb5ada6819c, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF