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F280039CSPZR

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersf280039cspzrfactory-2.0.0extractor-text
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Contents

README

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F280039CSPZR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

F280039CSPZR from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO28 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software, with digital input range VSS-0.3 V to VDDIO+0.3 V.
2 XRSn input Active-low device reset; driving it low (XRSn = 0) resets the device, and the internal pullup is always active.
3 VDDIO power_in 3.3-V digital I/O supply pin; recommended operating supply is 3.3 V nominal with 3.63 V maximum.
4 VDD power_in 1.2-V digital logic supply pin; recommended operating range is 1.14 V to 1.32 V.
5 VSS power_in Digital ground pin, which must be connected to board ground.
6 GPIO47 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
7 GPIO48 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
8 GPIO49 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
9 GPIO50 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
10 GPIO51 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
11 GPIO52 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
12 GPIO53 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
13 GPIO54 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
14 A6 input ADC analog input; must stay between VSSA-0.3 V and VDDA+0.3 V.
15 B2/C6 input ADC B/C analog input shared with CMPSS-3 positive input; must stay between VSSA-0.3 V and VDDA+0.3 V.
16 B3/VDAC passive Optional external reference voltage for on-chip COMPDACs; place at least a 1-µF capacitor if used as a DAC reference.
17 A2/B6/C9 input ADC analog input shared with CMPSS-1; must stay between VSSA-0.3 V and VDDA+0.3 V.
18 A3,B9,C7 input ADC analog input; must stay between VSSA-0.3 V and VDDA+0.3 V.
19 A14/B14/C4 input ADC analog input shared with CMPSS-3; must stay between VSSA-0.3 V and VDDA+0.3 V.
20 A11/B10/C0 input ADC analog input shared with CMPSS-1; must stay between VSSA-0.3 V and VDDA+0.3 V.
21 B12/C2 input ADC analog input shared with CMPSS-3; must stay between VSSA-0.3 V and VDDA+0.3 V.
22 A1/B7/DACB_OUT passive ADC analog input that also carries the buffered DAC-B output; analog input must stay between VSSA-0.3 V and VDDA+0.3 V.
23 A0/B15/C15/DACA_OUT passive ADC analog input that also carries the buffered DAC-A output; analog input must stay between VSSA-0.3 V and VDDA+0.3 V.
24 VREFHI input ADC high reference voltage; tie to VDDA if the ADC is not used.
25 VREFHI input ADC high reference voltage; tie to VDDA if the ADC is not used.
26 VREFLO input ADC low reference voltage; tie to VSSA when unused.
27 VREFLO input ADC low reference voltage; tie to VSSA when unused.
28 A12,C5 input ADC analog input; must stay between VSSA-0.3 V and VDDA+0.3 V.
29 C1 input CMPSS-4 analog input; must stay between VSSA-0.3 V and VDDA+0.3 V.
30 B11 input Analog input shared with CMPSS-4 and the GPIO21 AGPIO function; must stay between VSSA-0.3 V and VDDA+0.3 V.
31 A7/C3 input ADC analog input shared with CMPSS-4; must stay between VSSA-0.3 V and VDDA+0.3 V.
32 B5 input Analog input shared with CMPSS-1 and the GPIO20 AGPIO function; must stay between VSSA-0.3 V and VDDA+0.3 V.
33 VSSA power_in Analog ground pin; tie to VSS if an analog ground is not used.
34 VDDA power_in 3.3-V analog supply pin; place a minimum 2.2-µF decoupling capacitor on each pin.
35 A5 input ADC analog input shared with CMPSS-2; must stay between VSSA-0.3 V and VDDA+0.3 V.
36 A4/B8 input ADC analog input shared with CMPSS-2; must stay between VSSA-0.3 V and VDDA+0.3 V.
37 A8 input ADC analog input shared with CMPSS-4; must stay between VSSA-0.3 V and VDDA+0.3 V.
38 A9 input ADC analog input shared with CMPSS-2; must stay between VSSA-0.3 V and VDDA+0.3 V.
39 B4/C8 input ADC analog input shared with CMPSS-4; must stay between VSSA-0.3 V and VDDA+0.3 V.
40 A10/B1/C10 input ADC analog input shared with CMPSS-2; must stay between VSSA-0.3 V and VDDA+0.3 V.
41 B0/C11 input ADC analog input shared with CMPSS-2; must stay between VSSA-0.3 V and VDDA+0.3 V.
42 C14 input CMPSS-4 analog input; must stay between VSSA-0.3 V and VDDA+0.3 V.
43 GPIO55 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
44 GPIO60 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
45 VSS power_in Digital ground pin, which must be connected to board ground.
46 VDD power_in 1.2-V digital logic supply pin; recommended operating range is 1.14 V to 1.32 V.
47 VDDIO power_in 3.3-V digital I/O supply pin; recommended operating supply is 3.3 V nominal with 3.63 V maximum.
48 B5/GPIO20 bidirectional Analog-capable GPIO (AGPIO) pin; analog and digital functions are both disabled by default, and input must stay within VSSA-0.3 V to VDDA+0.3 V in analog use.
49 B11/GPIO21 bidirectional Analog-capable GPIO (AGPIO) pin; analog and digital functions are both disabled by default, and input must stay within VSSA-0.3 V to VDDA+0.3 V in analog use.
50 GPIO13 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
51 GPIO12 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
52 GPIO11 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
53 GPIO33 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
54 GPIO16 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
55 GPIO17 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
56 GPIO24 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
57 GPIO25 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
58 GPIO26 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
59 GPIO27 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
60 TCK input JTAG test clock input; the internal pullup is always active, and an external pullup or no connect is acceptable when unused.
61 GPIO37/TDO tri_state JTAG test data output (default mux); it is tri-stated when there is no JTAG activity, so a pullup should be enabled or added externally.
62 TMS input JTAG test mode select input; the internal pullup is always active and an external pullup resistor is recommended when unused.
63 GPIO35/TDI input JTAG test data input (default mux); the internal pullup is disabled by default and should be enabled or externally pulled up if used.
64 GPIO32 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
65 GPIO56 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
66 GPIO57 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
67 GPIO58 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
68 GPIO18/X2 bidirectional Crystal oscillator output (X2) when the crystal oscillator is used; otherwise a GPIO with pullup disabled at reset.
69 GPIO19/X1 bidirectional Crystal oscillator input or single-ended clock input (X1); the initialization software must configure this pin before the crystal oscillator is enabled.
70 VDDIO power_in 3.3-V digital I/O supply pin; recommended operating supply is 3.3 V nominal with 3.63 V maximum.
71 VDD power_in 1.2-V digital logic supply pin; recommended operating range is 1.14 V to 1.32 V.
72 VSS power_in Digital ground pin, which must be connected to board ground.
73 VREGENZ input Internal voltage regulator enable with internal pulldown; tie low to VSS to enable the internal VREG, or high to VDDIO to use an external supply.
74 GPIO8 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
75 GPIO4 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
76 GPIO3 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
77 GPIO2 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
78 GPIO1 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
79 GPIO0 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
80 GPIO40 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
81 GPIO23 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
82 GPIO41 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
83 GPIO22 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
84 GPIO7 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
85 GPIO44 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
86 VSS power_in Digital ground pin, which must be connected to board ground.
87 VDD power_in 1.2-V digital logic supply pin; recommended operating range is 1.14 V to 1.32 V.
88 VDDIO power_in 3.3-V digital I/O supply pin; recommended operating supply is 3.3 V nominal with 3.63 V maximum.
89 GPIO5 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
90 GPIO9 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
91 GPIO61 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
92 GPIO59 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
93 GPIO10 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
94 GPIO34 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
95 GPIO15 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
96 GPIO14 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
97 GPIO6 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
98 GPIO30 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
99 GPIO31 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.
100 GPIO29 bidirectional General-purpose digital I/O; pullup disabled at reset and enabled only by software.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDDIO with respect to VSS VDDIO -0.3 4.6 V with respect to VSS 59
Supply voltage VDDA with respect to VSSA VDDA -0.3 4.6 V with respect to VSSA 59
Supply voltage VDD with respect to VSS VDD -0.3 1.5 V with respect to VSS 59
Input voltage (3.3 V) VIN -0.3 4.6 V 59
Output voltage VO -0.3 4.6 V 59
Input clamp current, digital/analog input (per pin) IIK -20 20 mA VIN < VSS/VSSA or VIN > VDDIO/VDDA 59
Input clamp current, total for all inputs IIKTOTAL -20 20 mA VIN < VSS/VSSA or VIN > VDDIO/VDDA 59
Output current, digital output (per pin) IOUT -20 20 mA 59
Free-air temperature TA -40 125 °C 59
Operating junction temperature TJ -40 150 °C 59
Storage temperature Tstg -65 150 °C 59
Device supply voltage VDDIO and VDDA, internal BOR enabled VDDIO, VDDA 3.3 3.63 V Internal BOR enabled 60
Device supply voltage VDDIO and VDDA, internal BOR disabled VDDIO, VDDA 2.8 3.3 3.63 V Internal BOR disabled 60
Device supply voltage VDD VDD 1.14 1.2 1.32 V 60
Junction temperature TJ -40 150 °C 60
Free-air temperature TA -40 125 °C 60
Low-level output voltage VOL 0.4 V IOL = IOL MAX 68
Low-level output voltage VOL 0.2 V IOL = 100 µA 68
High-level output source current for all output pins IOH -4 mA 68
Low-level output sink current for all output pins IOL 4 mA 68
High-level output impedance for all output pins ROH 50 66 96 Ω VOH=VDDIO-0.4V 68
Low-level output impedance for all output pins ROL 48 60 84 Ω VOL=0.4V 68
High-level input voltage VIH 2 V 68
Low-level input voltage VIL 0.8 V 68
Input hysteresis VHYSTERESIS 125 mV 68
Input current, pins with pulldown IPULLDOWN 120 µA VDDIO = 3.3 V; VIN = VDDIO 68
Input current, digital inputs with pullup enabled IPULLUP 160 µA VDDIO = 3.3 V; VIN = 0 V 68
Weak pulldown resistance RPULLDOWN 22 31 62 kΩ 68
Weak pullup resistance RPULLUP 19 30 54 kΩ 68
Pin leakage, digital inputs ILEAK 0.1 µA 0 V ≤ VIN ≤ VDDIO; pullups and outputs disabled 68
Pin leakage, analog pins (except ADCINB3/VDAC) ILEAK 0.1 µA 0 V ≤ VIN ≤ VDDA; analog drivers disabled 68
Pin leakage, ADCINB3/VDAC ILEAK 0.2 4.4 µA 68
Input capacitance, digital inputs CI 2 pF 68
System current consumption, IDDIO operating mode IDDIO 80 108 mA Operating mode; TYP at Vnom, 30°C; CPU running from RAM, PLL enabled, SYSCLK max 61
System current consumption, IDDA operating mode IDDA 8 17.5 mA Operating mode; TYP at Vnom, 30°C 61
System current consumption, IDDIO idle mode IDDIO 30 58 mA Idle mode; TYP at Vnom, 30°C 61
System current consumption, IDDA idle mode IDDA 0.01 0.1 mA Idle mode; TYP at Vnom, 30°C 61
System current consumption, IDDIO standby mode IDDIO 16.5 41 mA Standby mode; TYP at Vnom, 30°C 61
System current consumption, IDDA standby mode IDDA 0.01 0.1 mA Standby mode; TYP at Vnom, 30°C 61
System current consumption, IDDIO halt mode IDDIO 12.5 36 mA Halt mode; TYP at Vnom, 30°C 62
System current consumption, IDDA halt mode IDDA 0.01 0.1 mA Halt mode; TYP at Vnom, 30°C 62
System current consumption, IDDIO flash erase/program IDDIO 72 106 mA Flash erase/program; PLL enabled, SYSCLK at 120 MHz; TYP at Vnom, 30°C 62
System current consumption, IDDA flash erase/program IDDA 0.1 2.5 mA Flash erase/program; TYP at Vnom, 30°C 62
Junction-to-case thermal resistance (PZ package) RΘJC 7.6 °C/W N/A airflow 69
Junction-to-board thermal resistance (PZ package) RΘJB 24.2 °C/W N/A airflow 69
Junction-to-free air thermal resistance, High-k PCB (PZ package) RΘJA 46.1 °C/W High-k PCB; 0 lfm 69
Junction-to-moving air thermal resistance (PZ package) RΘJMA 37.3 °C/W 150 lfm 69
Junction-to-moving air thermal resistance (PZ package) RΘJMA 34.8 °C/W 250 lfm 69
Junction-to-moving air thermal resistance (PZ package) RΘJMA 32.6 °C/W 500 lfm 69
Junction-to-package top thermal characterization (PZ package) PsiJT 0.2 °C/W 0 lfm 69
Junction-to-package top thermal characterization (PZ package) PsiJT 0.4 °C/W 150 lfm 69
Junction-to-package top thermal characterization (PZ package) PsiJT 0.6 °C/W 500 lfm 69
Junction-to-board thermal characterization (PZ package) PsiJB 23.8 °C/W 0 lfm 69
Junction-to-board thermal characterization (PZ package) PsiJB 22.8 °C/W 150 lfm 69
Junction-to-board thermal characterization (PZ package) PsiJB 22.4 °C/W 250 lfm 69
Junction-to-board thermal characterization (PZ package) PsiJB 21.9 °C/W 500 lfm 69

CAD (KiCad official)

  • Symbol: F280039CSPZR
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: f280039cspzr-etched.step / f280039cspzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); f280039cspzr.step / f280039cspzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (284 pp, sha256 c9f41b1092f6635f, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF