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F280039CSPM

Public Made by Adom

by adom

Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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F280039CSPM

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

F280039CSPM from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO29 bidirectional General-purpose I/O 29 (3.3 V VDDIO domain) with default GPIO function; muxed options include SCIA_TX, EPWM7_B, OUTPUTXBAR6, EQEP1_B, LINA_RX and AUXCLKIN.
2 GPIO28 bidirectional General-purpose I/O 28 (3.3 V VDDIO domain) with default GPIO function; muxed options include SCIA_RX, EPWM7_A, OUTPUTXBAR5, EQEP1_A and ERRORSTS.
3 XRSn bidirectional Open-drain device reset input and watchdog reset output with internal pullup; connect a 2.2 kΩ to 10 kΩ resistor between XRSn and VDDIO and a capacitor of 100 nF or less to VSS.
4 VDD power_in 1.2 V digital logic supply pin; recommended supply range is 1.14 V to 1.32 V, and VDD must be decoupled per the PMM section.
5 VSS power_in Digital ground; all VSS pins must be connected to the board ground.
6 A6 input ADC-A analog input 6 (also CMPSS-1 comparator input CMP1_HP2/CMP1_LP2 and analog pin AIO228); must stay below VDDA + 0.3 V.
7 B2,C6 input ADC-B analog input 2 and ADC-C analog input 6 (also CMPSS-3 inputs CMP3_HP0/CMP3_LP0 and analog pin AIO226); must stay below VDDA + 0.3 V.
8 A3,B3,C5,VDAC input ADC-A input 3 shared with ADC-B input 3, ADC-C input 5, and optional external reference VDAC for the on-chip DAC; VDAC needs at least a 1 µF capacitor when used as a DAC reference.
9 A2,B6,C9 input ADC-A input 2 shared with ADC-B input 6 and ADC-C input 9 (also CMPSS-1 inputs and analog pin AIO224); must stay below VDDA + 0.3 V.
10 A15,B9,C7 input ADC-A input 15 shared with ADC-B input 9 and ADC-C input 7 (also CMPSS-1 inputs and analog pin AIO233); must stay below VDDA + 0.3 V.
11 A14,B14,C4 input ADC-A input 14 shared with ADC-B input 14 and ADC-C input 4 (also CMPSS-3 inputs and analog pin AIO239); must stay below VDDA + 0.3 V.
12 A11,B10,C0 input ADC-A input 11 shared with ADC-B input 10 and ADC-C input 0 (also CMPSS-1 inputs and analog pin AIO237); must stay below VDDA + 0.3 V.
13 A5,B12,C2 input ADC-A input 5 shared with ADC-B input 12 and ADC-C input 2 (also CMPSS-2/CMPSS-3 inputs); must stay below VDDA + 0.3 V.
14 A1,B7,DACB_OUT input ADC-A input 1 shared with ADC-B input 7; also serves as buffered DAC-B output DACB_OUT and analog pin AIO232; must stay below VDDA + 0.3 V.
15 A0,B15,C15,DACA_OUT input ADC-A input 0 shared with ADC-B input 15 and ADC-C input 15; also serves as buffered DAC-A output DACA_OUT and analog pin AIO231; must stay below VDDA + 0.3 V.
16 VREFHI input ADC high reference voltage; driven externally in external reference mode or generated internally in internal reference mode, with at least a 2.2 µF capacitor between VREFHI and VREFLO placed close to the device.
17 VREFLO input ADC low reference voltage, tied to VSSA.
18 A12,C1 input ADC-A input 12 shared with ADC-C input 1 (also CMPSS-2 and CMPSS-4 inputs and analog pin AIO238/AIO248); must stay below VDDA + 0.3 V.
19 A7,C3 input ADC-A input 7 shared with ADC-C input 3 (also CMPSS-4 inputs and analog pin AIO245); must stay below VDDA + 0.3 V.
20 A8,B0,C11 input ADC-A input 8 shared with ADC-B input 0 and ADC-C input 11 (also CMPSS-4/CMPSS-2 inputs and analog pin AIO241/AIO253); must stay below VDDA + 0.3 V.
21 VSSA power_in Analog ground for the ADC, CMPSS, and DAC blocks.
22 VDDA power_in 3.3 V analog supply; place a minimum 2.2 µF decoupling capacitor on this pin.
23 A4,B8,C14 input ADC-A input 4 shared with ADC-B input 8 and ADC-C input 14 (also CMPSS-2/CMPSS-4 inputs and analog pin AIO225/AIO247); must stay below VDDA + 0.3 V.
24 A9,B4,C8 input ADC-A input 9 shared with ADC-B input 4 and ADC-C input 8 (also CMPSS-2/CMPSS-4 inputs and analog pin AIO227/AIO236); must stay below VDDA + 0.3 V.
25 A10,B1,C10 input ADC-A input 10 shared with ADC-B input 1 and ADC-C input 10 (also CMPSS-2 inputs and analog pin AIO230); must stay below VDDA + 0.3 V.
26 VSS power_in Digital ground; all VSS pins must be connected to the board ground.
27 VDD power_in 1.2 V digital logic supply pin; recommended supply range is 1.14 V to 1.32 V.
28 VDDIO power_in 3.3 V digital I/O supply pin; recommended range is 3.3 V nominal, 3.63 V maximum (2.8 V minimum with internal BOR disabled).
29 GPIO13 bidirectional General-purpose I/O 13 with default GPIO function; muxed options include EPWM7_B, MCAN_TX, EQEP1_INDEX, SCIB_RX, PMBUSA_ALERT and SPIA_SOMI.
30 GPIO12 bidirectional General-purpose I/O 12 with default GPIO function; muxed options include EPWM7_A, MCAN_RX, EQEP1_STROBE, SCIB_TX, PMBUSA_CTL and HIC_INT.
31 GPIO11 bidirectional General-purpose I/O 11 with default GPIO function; muxed options include EPWM6_B, SCIB_RX, EQEP1_B, SPIA_STE, LINB_RX and EQEP2_A.
32 GPIO33 bidirectional General-purpose I/O 33 with default GPIO function; muxed options include I2CA_SCL, SPIB_STE, OUTPUTXBAR4, LINA_RX, ADCSOCAO and CANA_RX.
33 GPIO16 bidirectional General-purpose I/O 16 with default GPIO function; muxed options include SPIA_SIMO, OUTPUTXBAR7, EPWM5_A, SCIA_TX, XCLKOUT and SPIB_SOMI.
34 GPIO17 bidirectional General-purpose I/O 17 with default GPIO function; muxed options include SPIA_SOMI, OUTPUTXBAR8, EPWM5_B, SCIA_RX, SD1_C1 and CANA_TX.
35 GPIO24 bidirectional General-purpose I/O 24 with default GPIO function; muxed options include OUTPUTXBAR1, EQEP2_A, EPWM8_A, SPIB_SIMO, ERRORSTS and SCIA_TX.
36 TCK input JTAG test clock with internal pullup enabled.
37 GPIO37/TDO tri_state JTAG test data output (TDO) by default; the pin is tri-stated when JTAG is inactive, so an internal or external pullup is needed to avoid a floating GPIO input. Also GPIO37 with muxed options such as OUTPUTXBAR2, I2CA_SCL and SCIA_TX.
38 TMS bidirectional JTAG test mode select with internal pullup; place an external pullup of about 2.2 kΩ to VDDIO to hold JTAG in reset during normal operation.
39 GPIO35/TDI input JTAG test data input (TDI) by default; enable the internal pullup or add an external pullup to avoid a floating input. Also GPIO35 with muxed options such as SCIA_RX, I2CA_SDA and CANA_RX.
40 GPIO32 bidirectional General-purpose I/O 32 with default GPIO function; muxed options include I2CA_SDA, SPIB_CLK, EPWM8_B, LINA_TX, SD1_D2 and HIC_INT.
41 GPIO18,X2 bidirectional General-purpose I/O 18, or crystal oscillator output X2 when the crystal is used; muxed options include SPIA_CLK, SCIB_TX, CANA_RX and EPWM6_A.
42 GPIO19,X1 bidirectional General-purpose I/O 19, or crystal oscillator/single-ended clock input X1; the initialization software must configure this pin before enabling the crystal oscillator.
43 VDDIO power_in 3.3 V digital I/O supply pin; recommended range is 3.3 V nominal, 3.63 V maximum.
44 VDD power_in 1.2 V digital logic supply pin; recommended supply range is 1.14 V to 1.32 V.
45 VSS power_in Digital ground; all VSS pins must be connected to the board ground.
46 GPIO39 bidirectional General-purpose I/O 39 with default GPIO function; muxed options include MCAN_RX, FSIRXA_CLK, EQEP2_INDEX, SYNCOUT, EQEP1_INDEX and HIC_D7.
47 GPIO8 bidirectional General-purpose I/O 8 with default GPIO function; muxed options include EPWM5_A, ADCSOCAO, SCIA_TX, SPIA_SIMO, I2CA_SCL and FSITXA_TDM_CLK.
48 GPIO4 bidirectional General-purpose I/O 4 with default GPIO function; muxed options include EPWM3_A, MCAN_TX, OUTPUTXBAR3, CANA_TX, SPIB_CLK and EQEP2_STROBE.
49 GPIO3 bidirectional General-purpose I/O 3 with default GPIO function; muxed options include EPWM2_B, OUTPUTXBAR2, PMBUSA_SCL, SPIA_CLK, SCIA_RX and CANA_RX.
50 GPIO2 bidirectional General-purpose I/O 2 with default GPIO function; muxed options include EPWM2_A, OUTPUTXBAR1, PMBUSA_SDA, SPIA_SIMO, SCIA_TX and CANA_TX.
51 GPIO1 bidirectional General-purpose I/O 1 with default GPIO function; muxed options include EPWM1_B, I2CA_SCL, SPIA_SOMI, MCAN_TX and HIC_D10.
52 GPIO0 bidirectional General-purpose I/O 0 with default GPIO function; muxed options include EPWM1_A, I2CA_SDA, SPIA_STE, FSIRXA_CLK, MCAN_RX and EQEP1_INDEX.
53 GPIO40 bidirectional General-purpose I/O 40 with default GPIO function; muxed options include SPIB_SIMO, EPWM2_B, PMBUSA_SDA, FSIRXA_D0, SCIB_TX and EQEP1_A.
54 GPIO23 bidirectional General-purpose I/O 23 with default GPIO function; muxed options include EQEP1_INDEX, SCIB_RX, SPIB_STE, SD1_C4, LINA_RX and EPWM4_B.
55 GPIO41 bidirectional General-purpose I/O 41 with default GPIO function; muxed options include EPWM2_A, PMBUSA_SCL, FSIRXA_D1, SCIB_RX, EQEP1_B and SPIB_SOMI.
56 GPIO22 bidirectional General-purpose I/O 22 with default GPIO function; muxed options include EQEP1_STROBE, SCIB_TX, SPIB_CLK, SD1_D4, LINA_TX and EPWM4_A.
57 GPIO7 bidirectional General-purpose I/O 7 with default GPIO function; muxed options include EPWM4_B, OUTPUTXBAR5, EQEP1_B, SPIB_SIMO, FSITXA_CLK and HIC_A6.
58 VSS power_in Digital ground; all VSS pins must be connected to the board ground.
59 VDD power_in 1.2 V digital logic supply pin; recommended supply range is 1.14 V to 1.32 V.
60 VDDIO power_in 3.3 V digital I/O supply pin; recommended range is 3.3 V nominal, 3.63 V maximum.
61 GPIO5 bidirectional General-purpose I/O 5 with default GPIO function; muxed options include EPWM3_B, OUTPUTXBAR3, MCAN_RX, CANA_RX, SPIA_STE and FSITXA_D1.
62 GPIO9 bidirectional General-purpose I/O 9 with default GPIO function; muxed options include EPWM5_B, SCIB_TX, OUTPUTXBAR6, EQEP1_INDEX, SCIA_RX and SPIA_CLK.
63 GPIO10 bidirectional General-purpose I/O 10 with default GPIO function; muxed options include EPWM6_A, ADCSOCBO, EQEP1_A, SCIB_TX, SPIA_SOMI and I2CA_SDA.
64 GPIO6 bidirectional General-purpose I/O 6 with default GPIO function; muxed options include EPWM4_A, OUTPUTXBAR4, SYNCOUT, EQEP1_A, SPIB_SOMI and FSITXA_D0.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

CAD (KiCad official)

  • Symbol: F280039CSPM
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: f280039cspm-etched.step / f280039cspm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); f280039cspm.step / f280039cspm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (285 pp, sha256 4385cb7a74ef5d7f, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF