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F280037CSPN

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersf280037cspnfactory-2.0.0extractor-text
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Contents

README

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F280037CSPN

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-80(12x12)

F280037CSPN from Texas Instruments, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO30 bidirectional General-purpose 3.3-V digital I/O GPIO30 with multiplexed peripheral functions; per-pin mux options are in Table 5-1, which is not in the provided text.
2 GPIO31 bidirectional General-purpose 3.3-V digital I/O GPIO31 with multiplexed peripheral functions; per-pin mux options are in Table 5-1, which is not in the provided text.
3 GPIO29 bidirectional General-purpose 3.3-V digital I/O GPIO29 with multiplexed peripheral functions; per-pin mux options are in Table 5-1, which is not in the provided text.
4 GPIO28 bidirectional General-purpose 3.3-V digital I/O GPIO28 with multiplexed peripheral functions; per-pin mux options are in Table 5-1, which is not in the provided text.
5 XRSn input Active-low device reset input with internal pullup always active; driving it low holds the device in reset.
6 GPIO46 bidirectional General-purpose 3.3-V digital I/O GPIO46 with multiplexed peripheral functions; per-pin mux options are in Table 5-1, which is not in the provided text.
7 VDDIO power_in 3.3-V digital I/O power pin; the recommended supply is 3.3 V nominal with a 3.3 V to 3.63 V range when internal BOR is enabled.
8 VDD power_in 1.2-V digital logic core power pin, recommended range 1.14 V to 1.32 V.
9 VSS power_in Digital ground pin that must be connected to board ground.
10 A6 passive ADC-A analog input 6 (also CMPSS-1 positive input path and digital-input-only AIO228).
11 B2,C6 passive ADC-B analog input 2 and ADC-C analog input 6, also usable as CMPSS-3 positive input 0 (AIO226).
12 A3,B3,C5,VDAC passive ADC-A input 3, ADC-B input 3 and VDAC optional external reference for the on-chip COMPDACs/GPDACs; at least 1 µF is required on VDAC if it is used as a DAC reference.
13 A2,B6,C9 passive ADC-A input 2, ADC-B input 6 and ADC-C input 9 (also CMPSS-1 positive input 0, AIO224).
14 A15,B9,C7 passive ADC-A input 15, ADC-B input 9 and ADC-C input 7; analog inputs must stay within VSSA − 0.3 V to VDDA + 0.3 V.
15 A14,B14,C4 passive ADC-A input 14, ADC-B input 14 and ADC-C input 4 (also CMPSS-3 positive input 4, AIO239).
16 A11,B10,C0 passive ADC-A input 11, ADC-B input 10 and ADC-C input 0 (also CMPSS-1 input 1, AIO237).
17 A5,B12,C2 passive ADC-A input 5, ADC-B input 12 and ADC-C input 2 (also CMPSS-2 positive input 5, AIO249).
18 A1,B7,DACB_OUT passive ADC-A input 1 and ADC-B input 7 shared with the buffered DAC-B output DACB_OUT; if a DACx_OUT pin is unused it may be left unconnected or tied to VSSA through a 4.7-kΩ or larger resistor.
19 A0,B15,C15,DACA_OUT passive ADC-A input 0, ADC-B input 15 and ADC-C input 15 shared with the buffered DAC-A output DACA_OUT; if unused it may be left unconnected or tied to VSSA through a 4.7-kΩ or larger resistor.
20 VREFHI input ADC high-side reference voltage input; tie to VDDA if the ADC is not used.
21 VREFLO input ADC low-side reference voltage input; tie to VSSA.
22 A12,C1 passive ADC-A input 12 and ADC-C input 1 analog inputs.
23 A7,C3 passive ADC-A input 7 and ADC-C input 3 analog inputs.
24 A8,B0,C11 passive ADC-A input 8, ADC-B input 0 and ADC-C input 11 analog inputs.
25 VSSA power_in Analog ground pin; tie to VSS if a separate analog ground is not used.
26 VDDA power_in 3.3-V analog power pin; place a minimum 2.2-µF decoupling capacitor on the pin, or tie to VDDIO if no dedicated analog supply is used.
27 A4,B8,C14 passive ADC-A input 4, ADC-B input 8 and ADC-C input 14 analog inputs.
28 A9,B4,C8 passive ADC-A input 9, ADC-B input 4 and ADC-C input 8 analog inputs.
29 A10,B1,C10 passive ADC-A input 10, ADC-B input 1 and ADC-C input 10 analog inputs.
30 VSS power_in Digital ground pin that must be connected to board ground.
31 VDD power_in 1.2-V digital logic core power pin, recommended range 1.14 V to 1.32 V.
32 VDDIO power_in 3.3-V digital I/O power pin; the recommended supply is 3.3 V nominal.
33 B5,GPIO20 bidirectional ADC-B input 5 shared with AGPIO20, which supports EQEP1_A, SPIB_SIMO, SD1_D3 and MCAN_TX functions; AGPIOs are unconnected (both analog and digital disabled) by default.
34 B11,GPIO21 bidirectional ADC-B input 11 shared with AGPIO21, which supports EQEP1_B, SPIB_SOMI, SD1_C3 and MCAN_RX functions; AGPIOs are unconnected by default.
35 GPIO13 bidirectional General-purpose I/O GPIO13 with muxed EPWM7_B, MCAN_TX, EQEP1_INDEX, SCIB_RX, PMBUSA_ALERT, FSIRXA_CLK, LINB_RX, SPIA_SOMI, CANA_TX, HIC_D11 and HIC_D5 functions.
36 GPIO12 bidirectional General-purpose I/O GPIO12 with muxed EPWM7_A, MCAN_RX, EQEP1_STROBE, SCIB_TX, PMBUSA_CTL, FSIRXA_D0, LINB_TX, SPIA_CLK, CANA_RX, HIC_D13 and HIC_INT functions.
37 GPIO11 bidirectional General-purpose I/O GPIO11 with muxed EPWM6_B, OUTPUTXBAR7, EQEP1_B, SCIB_RX, SPIA_STE, FSIRXA_D1, LINB_RX, EQEP2_A, SPIA_SIMO, HIC_D6 and HIC_NBE0 functions.
38 GPIO33 bidirectional General-purpose 3.3-V digital I/O GPIO33 with multiplexed peripheral functions; per-pin mux options are in Table 5-1, which is not in the provided text.
39 GPIO16 bidirectional General-purpose I/O GPIO16 with muxed SPIA_SIMO, OUTPUTXBAR7, EPWM5_A, SCIA_TX, SD1_D1, EQEP1_STROBE, PMBUSA_SCL, XCLKOUT, EQEP2_B, SPIB_SOMI and HIC_D1 functions.
40 GPIO17 bidirectional General-purpose I/O GPIO17 with muxed SPIA_SOMI, OUTPUTXBAR8, EPWM5_B, SCIA_RX, SD1_C1, EQEP1_INDEX, PMBUSA_SDA, CANA_TX and HIC_D2 functions.
41 GPIO24 bidirectional General-purpose I/O GPIO24 with muxed OUTPUTXBAR1, EQEP2_A, EPWM8_A, SPIB_SIMO, SD2_D1, LINB_TX, PMBUSA_SCL, SCIA_TX, ERRORSTS (requires an external pulldown) and HIC_D3 functions.
42 GPIO25 bidirectional General-purpose I/O GPIO25 with muxed OUTPUTXBAR2, EQEP2_B, EQEP1_A, SPIB_SOMI, SD2_C1, FSITXA_D1, PMBUSA_SDA, SCIA_RX and HIC_BASESEL0 functions.
43 GPIO26 bidirectional General-purpose 3.3-V digital I/O GPIO26 with multiplexed peripheral functions; per-pin mux options are in Table 5-1, which is not in the provided text.
44 GPIO27 bidirectional General-purpose 3.3-V digital I/O GPIO27 with multiplexed peripheral functions; per-pin mux options are in Table 5-1, which is not in the provided text.
45 TCK input JTAG test clock input with internal pullup always active; a pullup resistor or no connect is acceptable.
46 GPIO37/TDO tri_state JTAG test data output (default mux) that is tri-stated when there is no JTAG activity, so an internal or external pullup is needed to avoid a floating input.
47 TMS input JTAG test mode select input with internal pullup always active; an external pullup resistor is recommended.
48 GPIO35/TDI input JTAG test data input (default mux) with internal pullup disabled by default; enable the internal pullup or add an external pullup if used as TDI.
49 GPIO32 bidirectional General-purpose 3.3-V digital I/O GPIO32 with multiplexed peripheral functions; per-pin mux options are in Table 5-1, which is not in the provided text.
50 GPIO18/X2 bidirectional Crystal oscillator output X2 (alternate function) shared with GPIO18, whose other muxed functions include SPIA_CLK, SCIB_TX, CANA_RX, EPWM6_A and I2CA_SCL.
51 GPIO19/X1 bidirectional Crystal oscillator input or single-ended 3.3-V clock input (X1) shared with GPIO19; initialization software must configure this pin before enabling the crystal oscillator.
52 VDDIO power_in 3.3-V digital I/O power pin; the recommended supply is 3.3 V nominal.
53 VDD power_in 1.2-V digital logic core power pin, recommended range 1.14 V to 1.32 V.
54 GPIO43 bidirectional General-purpose 3.3-V digital I/O GPIO43 with multiplexed peripheral functions; per-pin mux options are in Table 5-1, which is not in the provided text.
55 VSS power_in Digital ground pin that must be connected to board ground.
56 GPIO39 bidirectional General-purpose 3.3-V digital I/O GPIO39 with multiplexed peripheral functions; per-pin mux options are in Table 5-1, which is not in the provided text.
57 GPIO42 bidirectional General-purpose 3.3-V digital I/O GPIO42 with multiplexed peripheral functions; per-pin mux options are in Table 5-1, which is not in the provided text.
58 GPIO8 bidirectional General-purpose 3.3-V digital I/O GPIO8 with multiplexed peripheral functions; per-pin mux options are in Table 5-1, which is not in the provided text.
59 GPIO4 bidirectional General-purpose 3.3-V digital I/O GPIO4 with multiplexed peripheral functions; per-pin mux options are in Table 5-1, which is not in the provided text.
60 GPIO3 bidirectional General-purpose 3.3-V digital I/O GPIO3 with multiplexed peripheral functions; per-pin mux options are in Table 5-1, which is not in the provided text.
61 GPIO2 bidirectional General-purpose 3.3-V digital I/O GPIO2 with multiplexed peripheral functions; per-pin mux options are in Table 5-1, which is not in the provided text.
62 GPIO1 bidirectional General-purpose 3.3-V digital I/O GPIO1 with multiplexed peripheral functions; per-pin mux options are in Table 5-1, which is not in the provided text.
63 GPIO0 bidirectional General-purpose 3.3-V digital I/O GPIO0 with multiplexed peripheral functions; per-pin mux options are in Table 5-1, which is not in the provided text.
64 GPIO40 bidirectional General-purpose 3.3-V digital I/O GPIO40 with multiplexed peripheral functions; per-pin mux options are in Table 5-1, which is not in the provided text.
65 GPIO23 bidirectional General-purpose I/O GPIO23 with muxed EQEP1_INDEX, SCIB_RX, SPIB_STE, SD1_C4, LINA_RX, CLB_OUTPUTXBAR3, LINB_RX, HIC_A3, EPWM4_B and HIC_D11 functions.
66 GPIO41 bidirectional General-purpose 3.3-V digital I/O GPIO41 with multiplexed peripheral functions; per-pin mux options are in Table 5-1, which is not in the provided text.
67 GPIO22 bidirectional General-purpose I/O GPIO22 with muxed EQEP1_STROBE, SCIB_TX, SPIB_CLK, SD1_D4, LINA_TX, CLB_OUTPUTXBAR1, LINB_TX, HIC_A5, EPWM4_A and HIC_D13 functions.
68 GPIO7 bidirectional General-purpose 3.3-V digital I/O GPIO7 with multiplexed peripheral functions; per-pin mux options are in Table 5-1, which is not in the provided text.
69 GPIO44 bidirectional General-purpose 3.3-V digital I/O GPIO44 with multiplexed peripheral functions; per-pin mux options are in Table 5-1, which is not in the provided text.
70 VSS power_in Digital ground pin that must be connected to board ground.
71 VDD power_in 1.2-V digital logic core power pin, recommended range 1.14 V to 1.32 V.
72 VDDIO power_in 3.3-V digital I/O power pin; the recommended supply is 3.3 V nominal.
73 GPIO45 bidirectional General-purpose 3.3-V digital I/O GPIO45 with multiplexed peripheral functions; per-pin mux options are in Table 5-1, which is not in the provided text.
74 GPIO5 bidirectional General-purpose 3.3-V digital I/O GPIO5 with multiplexed peripheral functions; per-pin mux options are in Table 5-1, which is not in the provided text.
75 GPIO9 bidirectional General-purpose I/O GPIO9 with muxed EPWM5_B, SCIB_TX, OUTPUTXBAR6, EQEP1_INDEX, SCIA_RX, SPIA_CLK, FSITXA_D0 and LINB_RX functions.
76 GPIO10 bidirectional General-purpose I/O GPIO10 with muxed EPWM6_A, ADCSOCBO, EQEP1_A, SCIB_TX, SPIA_SOMI, I2CA_SDA, FSITXA_CLK and LINB_TX functions.
77 GPIO34 bidirectional General-purpose 3.3-V digital I/O GPIO34 with multiplexed peripheral functions; per-pin mux options are in Table 5-1, which is not in the provided text.
78 GPIO15 bidirectional General-purpose I/O GPIO15 with muxed EPWM8_B, SCIB_RX, I2CB_SCL, OUTPUTXBAR4, PMBUSA_SCL, SPIB_STE, EQEP2_B, LINB_RX and HIC_D12 functions.
79 GPIO14 bidirectional General-purpose I/O GPIO14 with muxed EPWM8_A, SCIB_TX, I2CB_SDA, OUTPUTXBAR3, PMBUSA_SDA, SPIB_CLK, EQEP2_A, LINB_TX and HIC_D15 functions.
80 GPIO6 bidirectional General-purpose 3.3-V digital I/O GPIO6 with multiplexed peripheral functions; per-pin mux options are in Table 5-1, which is not in the provided text.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-80(12x12)
Category Embedded Processors & Controllers
Pins 80

CAD (KiCad official)

  • Symbol: F280037CSPN
  • Footprint: Package_QFP:LQFP-80_12x12mm_P0.5mm
  • 3D model: LQFP-80(12x12) (KiCad packages3D, STEP)
  • 3D model files: f280037cspn-etched.step / f280037cspn-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); f280037cspn.step / f280037cspn.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (277 pp, sha256 6d108fcb92967adf, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF