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F280025PNQR

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Contents

README

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F280025PNQR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-80(12x12)

F280025PNQR from Texas Instruments, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO30 bidirectional General-purpose I/O GPIO30 (default GPIO function) with muxed alternates including CANA_RX, SPIB_SIMO, EPWM1_A and HIC_D8; input qualification is selectable per GPIO.
2 GPIO31 bidirectional General-purpose I/O GPIO31 (default GPIO function) with muxed alternates including CANA_TX, SPIB_SOMI, EPWM1_B and FSIRXA_D1; input qualification is selectable per GPIO.
3 GPIO29 bidirectional General-purpose I/O GPIO29 (default GPIO function) with muxed alternates including SCIA_TX, EPWM7_B, EQEP1_B and HIC_NCS; input qualification is selectable per GPIO.
4 GPIO28 bidirectional General-purpose I/O GPIO28 (default GPIO function) with muxed alternates including SCIA_RX, EPWM7_A, EQEP1_A and HIC_NOE; input qualification is selectable per GPIO.
5 XRSn bidirectional Device reset input and watchdog reset output, open-drain with internal pull-up; a 2.2kΩ to 10kΩ resistor to VDDIO is recommended and any noise-filter capacitor should be 100nF or less.
6 GPIO46 bidirectional General-purpose I/O GPIO46 (default GPIO function) with muxed alternates including LINA_TX, FSITXA_D1 and HIC_NWE.
7 VDDIO power_in 3.3V digital I/O supply pin; all VDDIO pins must be connected per the power section.
8 VDD power_in 1.2V digital logic supply pin, generated by the internal VREG; decoupling capacitance on each VDD pin is required for VREG stability.
9 VSS power_in Digital ground pin, which must be connected to the board ground.
10 A6 input Analog input A6 (ADC-A channel not available on this pin; CMPSS-1 high/low comparator inputs and AIO228 digital input option), operating within VSSA to VDDA.
11 C6 input Analog input C6 associated with CMPSS-3 high/low comparator positive input 0 and AIO226 digital input option, operating within VSSA to VDDA.
12 A3/C5/VDAC input ADC-A input A3 and ADC-C input C5; VDAC is an optional external reference for the on-chip CMPSS DACs and needs at least one 1µF capacitor if used as reference.
13 A2/C9 input ADC-A input A2 and ADC-C input C9 with CMPSS-1 comparator inputs and AIO224 digital input option.
14 A15/C7 input ADC-A input A15 and ADC-C input C7 with CMPSS-1 comparator inputs and AIO233 digital input option.
15 A14/C4 input ADC-A input A14 and ADC-C input C4 with CMPSS-3 comparator inputs and AIO239 digital input option.
16 A11/C0 input ADC-A input A11 and ADC-C input C0 with CMPSS-1 comparator inputs and AIO237 digital input option.
17 A5/C2 input ADC-A input A5 and ADC-C input C2 with CMPSS-3 comparator inputs and AIO244 digital input option.
18 A1 input Analog input A1 with CMPSS-1 comparator input and AIO232 digital input option.
19 A0/C15 input ADC-A input A0 and ADC-C input C15 with CMPSS-3 comparator inputs and AIO231 digital input option.
20 VREFHI input ADC high reference voltage; drive externally in external reference mode, and place at least one 2.2µF capacitor between VREFHI and VREFLO as close to the device as possible, and keep it below VDDA + 0.3V.
21 VREFLO input ADC low reference voltage, connected to VSSA.
22 A12/C1 input ADC-A input A12 and ADC-C input C1 with CMPSS-2 and CMPSS-4 comparator inputs and AIO238 digital input option.
23 A7/C3 input ADC-A input A7 and ADC-C input C3 with CMPSS-4 comparator inputs and AIO245 digital input option.
24 A8/C11 input ADC-A input A8 and ADC-C input C11 with CMPSS-2 and CMPSS-4 comparator inputs and AIO241 digital input option.
25 VSSA power_in Analog ground pin.
26 VDDA power_in 3.3V analog supply pin; place a decoupling capacitor of at least 2.2µF on this pin.
27 A4/C14 input ADC-A input A4 and ADC-C input C14 with CMPSS-2 and CMPSS-4 comparator inputs and AIO225 digital input option.
28 A9/C8 input ADC-A input A9 and ADC-C input C8 with CMPSS-2 and CMPSS-4 comparator inputs and AIO227 digital input option.
29 A10/C10 input ADC-A input A10 and ADC-C input C10 with CMPSS-2 comparator inputs and AIO230 digital input option.
30 VSS power_in Digital ground pin, which must be connected to the board ground.
31 VDD power_in 1.2V digital logic supply pin, generated by the internal VREG; decoupling capacitance on each VDD pin is required for VREG stability.
32 VDDIO power_in 3.3V digital I/O supply pin; all VDDIO pins must be connected per the power section.
33 FLT2 unconnected Flash test pin 2 reserved for TI; must be left unconnected.
34 FLT1 unconnected Flash test pin 1 reserved for TI; must be left unconnected.
35 GPIO13 bidirectional General-purpose I/O GPIO13 (default GPIO function) with muxed alternates including EPWM7_B, PMBUSA_ALERT (open-drain), CANA_TX and HIC_D5.
36 GPIO12 bidirectional General-purpose I/O GPIO12 (default GPIO function) with muxed alternates including EPWM7_A, PMBUSA_CTL, CANA_RX and HIC_INT.
37 GPIO11 bidirectional General-purpose I/O GPIO11 (default GPIO function) with muxed alternates including EPWM6_B, EQEP1_B, SPIA_STE and HIC_NBE0.
38 GPIO33 bidirectional General-purpose I/O GPIO33 (open-drain I2CA_SCL alternate) with muxed alternates including SPIB_STE, LINA_RX, CANA_RX and ADCSOCAO.
39 GPIO16 bidirectional General-purpose I/O GPIO16 (default GPIO function) with muxed alternates including SPIA_SIMO, EPWM5_A, XCLKOUT and HIC_D1.
40 GPIO17 bidirectional General-purpose I/O GPIO17 (default GPIO function) with muxed alternates including SPIA_SOMI, EPWM5_B, CANA_TX and HIC_D2.
41 GPIO24 bidirectional General-purpose I/O GPIO24 (default GPIO function) with muxed alternates including OUTPUTXBAR1, SPIB_SIMO, SCIA_TX, ERRORSTS (external pull-down required when used) and HIC_D3.
42 GPIO25 bidirectional General-purpose I/O GPIO25 (default GPIO function) with muxed alternates including OUTPUTXBAR2, EQEP1_A, SCIA_RX and HIC_BASESEL0.
43 GPIO26 bidirectional General-purpose I/O GPIO26 (default GPIO function) with muxed alternates including OUTPUTXBAR3, SPIB_CLK, I2CA_SDA (open-drain) and HIC_A1.
44 GPIO27 bidirectional General-purpose I/O GPIO27 (default GPIO function) with muxed alternates including OUTPUTXBAR4, SPIB_STE, I2CA_SCL (open-drain) and HIC_A4.
45 TCK input JTAG test clock input with an internal pull-up.
46 GPIO37/TDO bidirectional JTAG test data output TDO is the default function; the internal pull-up is disabled by default and should be enabled or externally pulled up to avoid a floating input when used as GPIO37.
47 TMS bidirectional JTAG test mode select with an internal pull-up, sampled on TCK rising edge; a 2.2kΩ external pull-up to VDDIO is recommended and the device has no TRSTn pin.
48 GPIO35/TDI bidirectional JTAG test data input TDI is the default function; the internal pull-up is disabled by default and should be enabled or externally pulled up to avoid a floating input when used as TDI.
49 GPIO32 bidirectional General-purpose I/O GPIO32 (open-drain I2CA_SDA alternate) with muxed alternates including SPIB_CLK, LINA_TX, CANA_TX and ADCSOCBO.
50 GPIO18_X2 bidirectional General-purpose I/O GPIO18, also crystal oscillator output X2 when the crystal oscillator is enabled; used as GPIO when the oscillator is off.
51 GPIO19_X1 bidirectional General-purpose I/O GPIO19, also crystal oscillator or single-ended 3.3V clock input X1; must be configured by software before enabling the crystal oscillator.
52 VDDIO power_in 3.3V digital I/O supply pin; all VDDIO pins must be connected per the power section.
53 VDD power_in 1.2V digital logic supply pin, generated by the internal VREG; decoupling capacitance on each VDD pin is required for VREG stability.
54 GPIO43 bidirectional General-purpose I/O GPIO43 (open-drain PMBUSA_ALERT and I2CA_SCL alternates) with muxed alternates including OUTPUTXBAR6, EQEP1_INDEX, CLB_OUTPUTXBAR4 and HIC_A7.
55 VSS power_in Digital ground pin, which must be connected to the board ground.
56 GPIO39 bidirectional General-purpose I/O GPIO39 (default GPIO function) with muxed alternates including FSIRXA_CLK, EQEP2_INDEX, SYNCOUT and HIC_D7.
57 GPIO42 bidirectional General-purpose I/O GPIO42 (default GPIO function) with muxed alternates including LINA_RX, OUTPUTXBAR5, I2CA_SDA (open-drain) and HIC_A6.
58 GPIO8 bidirectional General-purpose I/O GPIO8 (default GPIO function) with muxed alternates including EPWM5_A, ADCSOCAO, SCIA_TX, I2CA_SCL (open-drain) and HIC_A0.
59 GPIO4 bidirectional General-purpose I/O GPIO4 (default GPIO function) with muxed alternates including EPWM3_A, OUTPUTXBAR3, CANA_TX, SPIB_CLK and HIC_NWE.
60 GPIO3 bidirectional General-purpose I/O GPIO3 (default GPIO function) with muxed alternates including EPWM2_B, OUTPUTXBAR2, PMBUSA_SCL (open-drain), SCIA_RX and HIC_NOE.
61 GPIO2 bidirectional General-purpose I/O GPIO2 (default GPIO function) with muxed alternates including EPWM2_A, PMBUSA_SDA (open-drain), SCIA_TX, CANA_TX and HIC_A1.
62 GPIO1 bidirectional General-purpose I/O GPIO1 (default GPIO function) with muxed alternates including EPWM1_B, I2CA_SCL (open-drain), SPIA_SOMI, CLB_OUTPUTXBAR7 and HIC_A2.
63 GPIO0 bidirectional General-purpose I/O GPIO0 (default GPIO function) with muxed alternates including EPWM1_A, I2CA_SDA (open-drain), SPIA_STE, FSIRXA_CLK and HIC_BASESEL1.
64 GPIO40 bidirectional General-purpose I/O GPIO40 (default GPIO function) with muxed alternates including SPIB_SIMO, EPWM2_B, PMBUSA_SDA (open-drain), FSIRXA_D0 and HIC_D5.
65 GPIO23 bidirectional General-purpose I/O GPIO23 (default GPIO function) with muxed alternates including EQEP1_INDEX, SPIB_STE, LINA_RX, LINB_RX and HIC_D11.
66 GPIO41 bidirectional General-purpose I/O GPIO41 (default GPIO function) with muxed alternates including EPWM2_A, PMBUSA_SCL (open-drain), FSIRXA_D1, EQEP1_B and HIC_D12.
67 GPIO22 bidirectional General-purpose I/O GPIO22 (default GPIO function) with muxed alternates including EQEP1_STROBE, SPIB_CLK, LINA_TX, CLB_OUTPUTXBAR1 and HIC_D13.
68 GPIO7 bidirectional General-purpose I/O GPIO7 (default GPIO function) with muxed alternates including EPWM4_B, OUTPUTXBAR5, EQEP1_B, SPIB_SIMO and HIC_A6.
69 GPIO44 bidirectional General-purpose I/O GPIO44 (default GPIO function) with muxed alternates including OUTPUTXBAR7, EQEP1_A, FSITXA_CLK, CLB_OUTPUTXBAR3 and HIC_D5.
70 VSS power_in Digital ground pin, which must be connected to the board ground.
71 VDD power_in 1.2V digital logic supply pin, generated by the internal VREG; decoupling capacitance on each VDD pin is required for VREG stability.
72 VDDIO power_in 3.3V digital I/O supply pin; all VDDIO pins must be connected per the power section.
73 GPIO45 bidirectional General-purpose I/O GPIO45 (default GPIO function) with muxed alternates including OUTPUTXBAR8, FSITXA_D0, CLB_OUTPUTXBAR4 and HIC_D6.
74 GPIO5 bidirectional General-purpose I/O GPIO5 (default GPIO function) with muxed alternates including EPWM3_B, OUTPUTXBAR3, CANA_RX, SPIA_STE and HIC_D15.
75 GPIO9 bidirectional General-purpose I/O GPIO9 (default GPIO function) with muxed alternates including EPWM5_B, OUTPUTXBAR6, EQEP1_INDEX, SCIA_RX and HIC_NRDY.
76 GPIO10 bidirectional General-purpose I/O GPIO10 (default GPIO function) with muxed alternates including EPWM6_A, ADCSOCBO, EQEP1_A, I2CA_SDA (open-drain) and HIC_NWE.
77 GPIO34 bidirectional General-purpose I/O GPIO34 (default GPIO function) with muxed alternates including OUTPUTXBAR1, PMBUSA_SDA (open-drain), I2CB_SDA (open-drain) and HIC_D9.
78 GPIO15 bidirectional General-purpose I/O GPIO15 (default GPIO function) with muxed alternates including I2CB_SCL (open-drain), OUTPUTXBAR4, PMBUSA_SCL (open-drain), EPWM3_B and HIC_D12.
79 GPIO14 bidirectional General-purpose I/O GPIO14 (default GPIO function) with muxed alternates including I2CB_SDA (open-drain), OUTPUTXBAR3, PMBUSA_SDA (open-drain), EPWM3_A and HIC_D15.
80 GPIO6 bidirectional General-purpose I/O GPIO6 (default GPIO function) with muxed alternates including EPWM4_A, OUTPUTXBAR4, SYNCOUT, EQEP1_A and HIC_D14.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-80(12x12)
Category Embedded Processors & Controllers
Pins 80

CAD (KiCad official)

  • Symbol: F280025PNQR
  • Footprint: Package_QFP:LQFP-80_12x12mm_P0.5mm
  • 3D model: LQFP-80(12x12) (KiCad packages3D, STEP)
  • 3D model files: f280025pnqr-etched.step / f280025pnqr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); f280025pnqr.step / f280025pnqr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (245 pp, sha256 0723d8e3e09e1f8b, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF