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F280025CPTSR

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.

componentembedded processors & controllersf280025cptsrfactory-2.0.0extractor-text
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Contents

README

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F280025CPTSR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

F280025CPTSR from Texas Instruments, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO29 bidirectional General-purpose digital I/O pin 29, individually programmable as input or output and multiplexable to an alternate peripheral function per the device pin-mux table.
2 GPIO28 bidirectional General-purpose digital I/O pin 28, individually programmable as input or output and multiplexable to an alternate peripheral function per the device pin-mux table.
3 XRSn bidirectional Active-low external reset pin used to reset the device; reflects internal reset sources such as the watchdog and brown-out reset circuit.
4 A6,C6 input ADC analog input channel A6, shared with CMPSS window-comparator analog input C6.
5 A3,C5,VDAC bidirectional ADC analog input channel A3, shared with CMPSS comparator input C5 and the internal 12-bit reference DAC analog output (VDAC).
6 A2,C9 input ADC analog input channel A2, shared with CMPSS window-comparator analog input C9.
7 A15,C7 input ADC analog input channel A15, shared with CMPSS window-comparator analog input C7.
8 A11,C0 input ADC analog input channel A11, shared with CMPSS window-comparator analog input C0.
9 A5,C2 input ADC analog input channel A5, shared with CMPSS window-comparator analog input C2.
10 A1 input Dedicated ADC analog input channel A1 (no comparator alternate function shown on this pin).
11 A0,C15 input ADC analog input channel A0, shared with CMPSS window-comparator analog input C15.
12 VREFHI power_in External high-side voltage reference input for the on-chip 12-bit ADCs.
13 VREFLO power_in External low-side (reference ground) voltage reference input for the on-chip 12-bit ADCs.
14 A12,C1 input ADC analog input channel A12, shared with CMPSS window-comparator analog input C1.
15 A7,C3 input ADC analog input channel A7, shared with CMPSS window-comparator analog input C3.
16 A8,C11 input ADC analog input channel A8, shared with CMPSS window-comparator analog input C11.
17 VSSA power_in Analog ground return pin for the ADC and analog subsystem.
18 VDDA power_in Analog power-supply pin for the ADC and analog subsystem, part of the single 3.3V device supply.
19 A4,C14 input ADC analog input channel A4, shared with CMPSS window-comparator analog input C14.
20 A9,C8 input ADC analog input channel A9, shared with CMPSS window-comparator analog input C8.
21 A10,C10 input ADC analog input channel A10, shared with CMPSS window-comparator analog input C10.
22 VSS power_in Digital ground/return pin.
23 GPIO13 bidirectional General-purpose digital I/O pin 13, individually programmable as input or output and multiplexable to an alternate peripheral function per the device pin-mux table.
24 GPIO12 bidirectional General-purpose digital I/O pin 12, individually programmable as input or output and multiplexable to an alternate peripheral function per the device pin-mux table.
25 GPIO33 bidirectional General-purpose digital I/O pin 33, individually programmable as input or output and multiplexable to an alternate peripheral function per the device pin-mux table.
26 GPIO16 bidirectional General-purpose digital I/O pin 16, individually programmable as input or output and multiplexable to an alternate peripheral function per the device pin-mux table.
27 GPIO24 bidirectional General-purpose digital I/O pin 24, individually programmable as input or output and multiplexable to an alternate peripheral function per the device pin-mux table.
28 TCK input Dedicated JTAG test clock input pin for the IEEE 1149.1 debug/test interface.
29 GPIO37/TDO bidirectional General-purpose digital I/O pin 37, alternately configurable as the JTAG test data output (TDO) of the debug/test interface.
30 TMS input Dedicated JTAG test mode select input pin for the IEEE 1149.1 debug/test interface.
31 GPIO35/TDI bidirectional General-purpose digital I/O pin 35, alternately configurable as the JTAG test data input (TDI) of the debug/test interface.
32 GPIO32 bidirectional General-purpose digital I/O pin 32, individually programmable as input or output and multiplexable to an alternate peripheral function per the device pin-mux table.
33 GPIO18_X2 bidirectional General-purpose digital I/O pin 18, alternately configurable as the X2 crystal-oscillator output terminal.
34 GPIO19_X1 bidirectional General-purpose digital I/O pin 19, alternately configurable as the X1 crystal-oscillator input terminal.
35 VDDIO power_in Digital I/O power-supply pin, part of the single 3.3V device supply that powers the GPIO buffers.
36 VDD power_in Digital core power-supply pin, part of the single 3.3V device supply; internal VREG derives the core logic voltage from this rail.
37 VSS power_in Digital ground/return pin.
38 GPIO4 bidirectional General-purpose digital I/O pin 4, individually programmable as input or output and multiplexable to an alternate peripheral function per the device pin-mux table.
39 GPIO3 bidirectional General-purpose digital I/O pin 3, individually programmable as input or output and multiplexable to an alternate peripheral function per the device pin-mux table.
40 GPIO2 bidirectional General-purpose digital I/O pin 2, individually programmable as input or output and multiplexable to an alternate peripheral function per the device pin-mux table.
41 GPIO1 bidirectional General-purpose digital I/O pin 1, individually programmable as input or output and multiplexable to an alternate peripheral function per the device pin-mux table.
42 GPIO0 bidirectional General-purpose digital I/O pin 0, individually programmable as input or output and multiplexable to an alternate peripheral function per the device pin-mux table.
43 GPIO7 bidirectional General-purpose digital I/O pin 7, individually programmable as input or output and multiplexable to an alternate peripheral function per the device pin-mux table.
44 VSS power_in Digital ground/return pin.
45 VDD power_in Digital core power-supply pin, part of the single 3.3V device supply with internal VREG generating the core logic voltage.
46 VDDIO power_in Digital I/O power-supply pin, part of the single 3.3V device supply that powers the GPIO buffers.
47 GPIO5 bidirectional General-purpose digital I/O pin 5, individually programmable as input or output and multiplexable to an alternate peripheral function per the device pin-mux table.
48 GPIO6 bidirectional General-purpose digital I/O pin 6, individually programmable as input or output and multiplexable to an alternate peripheral function per the device pin-mux table.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

CAD (KiCad official)

  • Symbol: F280025CPTSR
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: f280025cptsr-etched.step / f280025cptsr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); f280025cptsr.step / f280025cptsr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (245 pp, sha256 0723d8e3e09e1f8b, retrieved 2026-09-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-sonnet-5 (text+vision), consensus claude-opus-4-8 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF