F280025CPMQR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

F280025CPMQR from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GPIO29	bidirectional	General-purpose I/O 29, configured as an input with internal pull-up disabled at reset; alternates include SCIA_TX, EPWM7_B, OUTPUTXBAR6, EQEP1_B, EQEP2_INDEX, LINA_RX, SPIB_STE, ERRORSTS, I2CB_SCL and HIC_NCS.
2	GPIO28	bidirectional	General-purpose I/O 28, configured as an input with internal pull-up disabled at reset; alternates include SCIA_RX, EPWM7_A, OUTPUTXBAR5, EQEP1_A, EQEP2_STROBE, LINA_TX, SPIB_CLK, ERRORSTS, I2CB_SDA and HIC_NOE.
3	XRSn	bidirectional	Device reset input and watchdog reset output; open-drain with internal pull-up, a 2.2 kΩ to 10 kΩ resistor to VDDIO is recommended and any noise-filter capacitor to VSS should be 100 nF or less.
4	VDD	power_in	1.2 V digital logic supply pin; decoupling is required per the power management module section (VDD is generated internally by VREG).
5	VSS	power_in	Digital ground pin.
6	A6	input	Analog input (ADC-A input, multiplexed with CMPSS-1 comparator inputs and AIO228 digital input); shared with analog group, see Table 5-1 for limits.
7	C6	input	Analog input (ADC-C input, multiplexed with CMPSS-3 comparator inputs and AIO226 digital input).
8	A3/C5/VDAC	input	ADC-A input 3 / ADC-C input 5, and optional external reference for the on-chip CMPSS DAC; an internal capacitor to VSSA is always present, and at least one 1 µF capacitor is required if this pin is used as the DAC reference.
9	A2/C9	input	ADC-A input 2 / ADC-C input 9, also CMPSS-1 comparator inputs and AIO224.
10	A15/C7	input	ADC-A input 15 / ADC-C input 7, also CMPSS-1 comparator inputs and AIO233.
11	A14/C4	input	ADC-A input 14 / ADC-C input 4, also CMPSS-3 comparator inputs and AIO239.
12	A11/C0	input	ADC-A input 11 / ADC-C input 0, also CMPSS-1 comparator inputs and AIO237.
13	A5/C2	input	ADC-A input 5 / ADC-C input 2, also CMPSS-3 comparator inputs and AIO244.
14	A1	input	Analog input, also CMPSS-1 comparator inputs and AIO232.
15	A0/C15	input	ADC-A input 0 / ADC-C input 15, also CMPSS-3 comparator inputs and AIO231.
16	VREFHI	input	ADC high reference voltage; driven externally in external-reference mode or by the device in internal-reference mode, with at least one 2.2 µF capacitor placed between VREFHI and VREFLO as close to the device as possible.
17	VREFLO	input	ADC low reference voltage, to be connected to VSSA.
18	A12/C1	input	ADC-A input 12 / ADC-C input 1, also CMPSS-2 and CMPSS-4 comparator inputs and AIO238.
19	A7/C3	input	ADC-A input 7 / ADC-C input 3, also CMPSS-4 comparator inputs and AIO245.
20	A8/C11	input	ADC-A input 8 / ADC-C input 11, also CMPSS-2 and CMPSS-4 comparator inputs and AIO241.
21	VSSA	power_in	Analog ground pin for the ADC and CMPSS.
22	VDDA	power_in	3.3 V analog supply pin; place a decoupling capacitor of at least 2.2 µF on this pin.
23	A4/C14	input	ADC-A input 4 / ADC-C input 14, also CMPSS-2, CMPSS-4 comparator inputs and AIO225.
24	A9/C8	input	ADC-A input 9 / ADC-C input 8, also CMPSS-2 and CMPSS-4 comparator inputs and AIO227.
25	A10/C10	input	ADC-A input 10 / ADC-C input 10, also CMPSS-2 comparator inputs and AIO230.
26	VSS	power_in	Digital ground pin.
27	VDD	power_in	1.2 V digital logic supply pin.
28	VDDIO	power_in	3.3 V digital I/O supply pin.
29	GPIO13	bidirectional	General-purpose I/O 13 (default GPIO); alternates include EPWM7_B, EQEP1_INDEX, PMBUSA_ALERT (open-drain), FSIRXA_CLK, LINB_RX, SPIA_SOMI, CANA_TX, HIC_D11 and HIC_D5.
30	GPIO12	bidirectional	General-purpose I/O 12 (default GPIO); alternates include EPWM7_A, EQEP1_STROBE, PMBUSA_CTL, FSIRXA_D0, LINB_TX, SPIA_CLK, CANA_RX, HIC_D13 and HIC_INT.
31	GPIO11	bidirectional	General-purpose I/O 11 (default GPIO); alternates include EPWM6_B, OUTPUTXBAR7, EQEP1_B, SPIA_STE, FSIRXA_D1, LINB_RX, EQEP2_A, SPIA_SIMO, HIC_D6 and HIC_NBE0.
32	GPIO33	bidirectional	General-purpose I/O 33 (default GPIO); alternates include I2CA_SCL (open-drain), SPIB_STE, OUTPUTXBAR4, LINA_RX, FSIRXA_CLK, CANA_RX, EQEP2_B, ADCSOCAO and HIC_D0.
33	GPIO16	bidirectional	General-purpose I/O 16 (default GPIO); alternates include SPIA_SIMO, OUTPUTXBAR7, EPWM5_A, SCIA_TX, EQEP1_STROBE, PMBUSA_SCL (open-drain), XCLKOUT, EQEP2_B, SPIB_SOMI and HIC_D1.
34	GPIO17	bidirectional	General-purpose I/O 17 (default GPIO); alternates include SPIA_SOMI, OUTPUTXBAR8, EPWM5_B, SCIA_RX, EQEP1_INDEX, PMBUSA_SDA (open-drain), CANA_TX and HIC_D2.
35	GPIO24	bidirectional	General-purpose I/O 24 (default GPIO); alternates include OUTPUTXBAR1, EQEP2_A, SPIB_SIMO, LINB_TX, PMBUSA_SCL (open-drain), SCIA_TX, ERRORSTS (requires external pull-down when used) and HIC_D3.
36	TCK	input	JTAG test clock input with internal pull-up enabled; this pin does not have a TRSTn companion.
37	GPIO37/TDO	tri_state	JTAG test data output (default function); tri-stated when no JTAG activity, so an internal pull-up should be enabled or an external pull-up added to avoid a floating GPIO input; alternates include GPIO37 OUTPUTXBAR2, I2CA_SCL, SCIA_TX, CANA_TX, LINA_TX, EQEP1_B, PMBUSA_ALERT and HIC_NRDY.
38	TMS	bidirectional	JTAG test mode select input with internal pull-up; an external 2.2 kΩ pull-up to VDDIO is recommended to hold JTAG in reset during normal operation.
39	GPIO35/TDI	input	JTAG test data input (default function); internal pull-up is disabled by default, so an internal or external pull-up should be used to avoid a floating input; in cJTAG mode this pin is available as GPIO35.
40	GPIO32	bidirectional	General-purpose I/O 32 (default GPIO); alternates include I2CA_SDA (open-drain), SPIB_CLK, LINA_TX, FSIRXA_D0, CANA_TX, ADCSOCBO and HIC_INT.
41	GPIO18_X2	bidirectional	General-purpose I/O 18 / crystal oscillator output X2 (ALT function); used as X2 when the XTAL oscillator is enabled, and GPIO18 otherwise.
42	GPIO19_X1	bidirectional	General-purpose I/O 19 / crystal oscillator or single-ended clock input X1 (ALT function); the device initialization software must configure this pin before enabling the crystal oscillator.
43	VDDIO	power_in	3.3 V digital I/O supply pin.
44	VDD	power_in	1.2 V digital logic supply pin.
45	VSS	power_in	Digital ground pin.
46	GPIO39	bidirectional	General-purpose I/O 39 (default GPIO); alternates include FSIRXA_CLK, EQEP2_INDEX, CLB_OUTPUTXBAR2, SYNCOUT, EQEP1_INDEX and HIC_D7.
47	GPIO8	bidirectional	General-purpose I/O 8 (default GPIO); alternates include EPWM5_A, ADCSOCAO, EQEP1_STROBE, SCIA_TX, SPIA_SIMO, I2CA_SCL (open-drain), FSITXA_D1, CLB_OUTPUTXBAR5, HIC_A0, FSITXA_TDM_CLK and HIC_D8.
48	GPIO4	bidirectional	General-purpose I/O 4 (default GPIO); alternates include EPWM3_A, OUTPUTXBAR3, CANA_TX, SPIB_CLK, EQEP2_STROBE, FSIRXA_CLK, CLB_OUTPUTXBAR6, HIC_BASESEL2 and HIC_NWE.
49	GPIO3	bidirectional	General-purpose I/O 3 (default GPIO); alternates include EPWM2_B, OUTPUTXBAR2, PMBUSA_SCL (open-drain), SPIA_CLK, SCIA_RX, FSIRXA_D0, I2CB_SCL (open-drain), HIC_NOE, CANA_RX and HIC_D4.
50	GPIO2	bidirectional	General-purpose I/O 2 (default GPIO); alternates include EPWM2_A, OUTPUTXBAR1, PMBUSA_SDA (open-drain), SPIA_SIMO, SCIA_TX, FSIRXA_D1, I2CB_SDA (open-drain), HIC_A1, CANA_TX and HIC_D9.
51	GPIO1	bidirectional	General-purpose I/O 1 (default GPIO); alternates include EPWM1_B, I2CA_SCL (open-drain), SPIA_SOMI, CLB_OUTPUTXBAR7, HIC_A2, FSITXA_TDM_D1, and HIC_D10.
52	GPIO0	bidirectional	General-purpose I/O 0 (default GPIO); alternates include EPWM1_A, I2CA_SDA (open-drain), SPIA_STE, FSIRXA_CLK, CLB_OUTPUTXBAR8 and HIC_BASESEL1.
53	GPIO40	bidirectional	General-purpose I/O 40 (default GPIO); alternates include SPIB_SIMO, EPWM2_B, PMBUSA_SDA (open-drain), FSIRXA_D0, EQEP1_A, LINB_TX, HIC_NBE1 and HIC_D5.
54	GPIO23	bidirectional	General-purpose I/O 23 (default GPIO); alternates include EQEP1_INDEX, SPIB_STE, LINA_RX, LINB_RX, HIC_A3, EPWM4_B and HIC_D11.
55	GPIO41	bidirectional	General-purpose I/O 41 (default GPIO); alternates include EPWM2_A, PMBUSA_SCL (open-drain), FSIRXA_D1, EQEP1_B, LINB_RX, HIC_A4, SPIB_SOMI and HIC_D12.
56	GPIO22	bidirectional	General-purpose I/O 22 (default GPIO); alternates include EQEP1_STROBE, SPIB_CLK, LINA_TX, CLB_OUTPUTXBAR1, LINB_TX, HIC_A5, EPWM4_A and HIC_D13.
57	GPIO7	bidirectional	General-purpose I/O 7 (default GPIO); alternates include EPWM4_B, OUTPUTXBAR5, EQEP1_B, SPIB_SIMO, FSITXA_CLK, CLB_OUTPUTXBAR2, HIC_A6 and HIC_D14.
58	VSS	power_in	Digital ground pin.
59	VDD	power_in	1.2 V digital logic supply pin.
60	VDDIO	power_in	3.3 V digital I/O supply pin.
61	GPIO5	bidirectional	General-purpose I/O 5 (default GPIO); alternates include EPWM3_B, OUTPUTXBAR3, CANA_RX, SPIA_STE, FSITXA_D1, CLB_OUTPUTXBAR5, HIC_A7, HIC_D4 and HIC_D15.
62	GPIO9	bidirectional	General-purpose I/O 9 (default GPIO); alternates include EPWM5_B, OUTPUTXBAR6, EQEP1_INDEX, SCIA_RX, SPIA_CLK, FSITXA_D0, LINB_RX, HIC_BASESEL0, I2CB_SCL (open-drain) and HIC_NRDY.
63	GPIO10	bidirectional	General-purpose I/O 10 (default GPIO); alternates include EPWM6_A, ADCSOCBO, EQEP1_A, SPIA_SOMI, I2CA_SDA (open-drain), FSITXA_CLK, LINB_TX, HIC_NWE and FSITXA_TDM_D0.
64	GPIO6	bidirectional	General-purpose I/O 6 (default GPIO); alternates include EPWM4_A, OUTPUTXBAR4, SYNCOUT, EQEP1_A, SPIB_SOMI, FSITXA_D0, FSITXA_D1, HIC_NBE1, CLB_OUTPUTXBAR8 and HIC_D14.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	LQFP-64(10x10)
Category	Embedded Processors & Controllers
Pins	64

CAD (KiCad official)

Symbol: F280025CPMQR
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: f280025cpmqr-etched.step / f280025cpmqr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); f280025cpmqr.step / f280025cpmqr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (245 pp, sha256 0723d8e3e09e1f8b, retrieved 2026-10-12, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# F280025CPMQR

**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

F280025CPMQR from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GPIO29 | bidirectional | General-purpose I/O 29, configured as an input with internal pull-up disabled at reset; alternates include SCIA_TX, EPWM7_B, OUTPUTXBAR6, EQEP1_B, EQEP2_INDEX, LINA_RX, SPIB_STE, ERRORSTS, I2CB_SCL and HIC_NCS. |
| 2 | GPIO28 | bidirectional | General-purpose I/O 28, configured as an input with internal pull-up disabled at reset; alternates include SCIA_RX, EPWM7_A, OUTPUTXBAR5, EQEP1_A, EQEP2_STROBE, LINA_TX, SPIB_CLK, ERRORSTS, I2CB_SDA and HIC_NOE. |
| 3 | XRSn | bidirectional | Device reset input and watchdog reset output; open-drain with internal pull-up, a 2.2 kΩ to 10 kΩ resistor to VDDIO is recommended and any noise-filter capacitor to VSS should be 100 nF or less. |
| 4 | VDD | power_in | 1.2 V digital logic supply pin; decoupling is required per the power management module section (VDD is generated internally by VREG). |
| 5 | VSS | power_in | Digital ground pin. |
| 6 | A6 | input | Analog input (ADC-A input, multiplexed with CMPSS-1 comparator inputs and AIO228 digital input); shared with analog group, see Table 5-1 for limits. |
| 7 | C6 | input | Analog input (ADC-C input, multiplexed with CMPSS-3 comparator inputs and AIO226 digital input). |
| 8 | A3/C5/VDAC | input | ADC-A input 3 / ADC-C input 5, and optional external reference for the on-chip CMPSS DAC; an internal capacitor to VSSA is always present, and at least one 1 µF capacitor is required if this pin is used as the DAC reference. |
| 9 | A2/C9 | input | ADC-A input 2 / ADC-C input 9, also CMPSS-1 comparator inputs and AIO224. |
| 10 | A15/C7 | input | ADC-A input 15 / ADC-C input 7, also CMPSS-1 comparator inputs and AIO233. |
| 11 | A14/C4 | input | ADC-A input 14 / ADC-C input 4, also CMPSS-3 comparator inputs and AIO239. |
| 12 | A11/C0 | input | ADC-A input 11 / ADC-C input 0, also CMPSS-1 comparator inputs and AIO237. |
| 13 | A5/C2 | input | ADC-A input 5 / ADC-C input 2, also CMPSS-3 comparator inputs and AIO244. |
| 14 | A1 | input | Analog input, also CMPSS-1 comparator inputs and AIO232. |
| 15 | A0/C15 | input | ADC-A input 0 / ADC-C input 15, also CMPSS-3 comparator inputs and AIO231. |
| 16 | VREFHI | input | ADC high reference voltage; driven externally in external-reference mode or by the device in internal-reference mode, with at least one 2.2 µF capacitor placed between VREFHI and VREFLO as close to the device as possible. |
| 17 | VREFLO | input | ADC low reference voltage, to be connected to VSSA. |
| 18 | A12/C1 | input | ADC-A input 12 / ADC-C input 1, also CMPSS-2 and CMPSS-4 comparator inputs and AIO238. |
| 19 | A7/C3 | input | ADC-A input 7 / ADC-C input 3, also CMPSS-4 comparator inputs and AIO245. |
| 20 | A8/C11 | input | ADC-A input 8 / ADC-C input 11, also CMPSS-2 and CMPSS-4 comparator inputs and AIO241. |
| 21 | VSSA | power_in | Analog ground pin for the ADC and CMPSS. |
| 22 | VDDA | power_in | 3.3 V analog supply pin; place a decoupling capacitor of at least 2.2 µF on this pin. |
| 23 | A4/C14 | input | ADC-A input 4 / ADC-C input 14, also CMPSS-2, CMPSS-4 comparator inputs and AIO225. |
| 24 | A9/C8 | input | ADC-A input 9 / ADC-C input 8, also CMPSS-2 and CMPSS-4 comparator inputs and AIO227. |
| 25 | A10/C10 | input | ADC-A input 10 / ADC-C input 10, also CMPSS-2 comparator inputs and AIO230. |
| 26 | VSS | power_in | Digital ground pin. |
| 27 | VDD | power_in | 1.2 V digital logic supply pin. |
| 28 | VDDIO | power_in | 3.3 V digital I/O supply pin. |
| 29 | GPIO13 | bidirectional | General-purpose I/O 13 (default GPIO); alternates include EPWM7_B, EQEP1_INDEX, PMBUSA_ALERT (open-drain), FSIRXA_CLK, LINB_RX, SPIA_SOMI, CANA_TX, HIC_D11 and HIC_D5. |
| 30 | GPIO12 | bidirectional | General-purpose I/O 12 (default GPIO); alternates include EPWM7_A, EQEP1_STROBE, PMBUSA_CTL, FSIRXA_D0, LINB_TX, SPIA_CLK, CANA_RX, HIC_D13 and HIC_INT. |
| 31 | GPIO11 | bidirectional | General-purpose I/O 11 (default GPIO); alternates include EPWM6_B, OUTPUTXBAR7, EQEP1_B, SPIA_STE, FSIRXA_D1, LINB_RX, EQEP2_A, SPIA_SIMO, HIC_D6 and HIC_NBE0. |
| 32 | GPIO33 | bidirectional | General-purpose I/O 33 (default GPIO); alternates include I2CA_SCL (open-drain), SPIB_STE, OUTPUTXBAR4, LINA_RX, FSIRXA_CLK, CANA_RX, EQEP2_B, ADCSOCAO and HIC_D0. |
| 33 | GPIO16 | bidirectional | General-purpose I/O 16 (default GPIO); alternates include SPIA_SIMO, OUTPUTXBAR7, EPWM5_A, SCIA_TX, EQEP1_STROBE, PMBUSA_SCL (open-drain), XCLKOUT, EQEP2_B, SPIB_SOMI and HIC_D1. |
| 34 | GPIO17 | bidirectional | General-purpose I/O 17 (default GPIO); alternates include SPIA_SOMI, OUTPUTXBAR8, EPWM5_B, SCIA_RX, EQEP1_INDEX, PMBUSA_SDA (open-drain), CANA_TX and HIC_D2. |
| 35 | GPIO24 | bidirectional | General-purpose I/O 24 (default GPIO); alternates include OUTPUTXBAR1, EQEP2_A, SPIB_SIMO, LINB_TX, PMBUSA_SCL (open-drain), SCIA_TX, ERRORSTS (requires external pull-down when used) and HIC_D3. |
| 36 | TCK | input | JTAG test clock input with internal pull-up enabled; this pin does not have a TRSTn companion. |
| 37 | GPIO37/TDO | tri_state | JTAG test data output (default function); tri-stated when no JTAG activity, so an internal pull-up should be enabled or an external pull-up added to avoid a floating GPIO input; alternates include GPIO37 OUTPUTXBAR2, I2CA_SCL, SCIA_TX, CANA_TX, LINA_TX, EQEP1_B, PMBUSA_ALERT and HIC_NRDY. |
| 38 | TMS | bidirectional | JTAG test mode select input with internal pull-up; an external 2.2 kΩ pull-up to VDDIO is recommended to hold JTAG in reset during normal operation. |
| 39 | GPIO35/TDI | input | JTAG test data input (default function); internal pull-up is disabled by default, so an internal or external pull-up should be used to avoid a floating input; in cJTAG mode this pin is available as GPIO35. |
| 40 | GPIO32 | bidirectional | General-purpose I/O 32 (default GPIO); alternates include I2CA_SDA (open-drain), SPIB_CLK, LINA_TX, FSIRXA_D0, CANA_TX, ADCSOCBO and HIC_INT. |
| 41 | GPIO18_X2 | bidirectional | General-purpose I/O 18 / crystal oscillator output X2 (ALT function); used as X2 when the XTAL oscillator is enabled, and GPIO18 otherwise. |
| 42 | GPIO19_X1 | bidirectional | General-purpose I/O 19 / crystal oscillator or single-ended clock input X1 (ALT function); the device initialization software must configure this pin before enabling the crystal oscillator. |
| 43 | VDDIO | power_in | 3.3 V digital I/O supply pin. |
| 44 | VDD | power_in | 1.2 V digital logic supply pin. |
| 45 | VSS | power_in | Digital ground pin. |
| 46 | GPIO39 | bidirectional | General-purpose I/O 39 (default GPIO); alternates include FSIRXA_CLK, EQEP2_INDEX, CLB_OUTPUTXBAR2, SYNCOUT, EQEP1_INDEX and HIC_D7. |
| 47 | GPIO8 | bidirectional | General-purpose I/O 8 (default GPIO); alternates include EPWM5_A, ADCSOCAO, EQEP1_STROBE, SCIA_TX, SPIA_SIMO, I2CA_SCL (open-drain), FSITXA_D1, CLB_OUTPUTXBAR5, HIC_A0, FSITXA_TDM_CLK and HIC_D8. |
| 48 | GPIO4 | bidirectional | General-purpose I/O 4 (default GPIO); alternates include EPWM3_A, OUTPUTXBAR3, CANA_TX, SPIB_CLK, EQEP2_STROBE, FSIRXA_CLK, CLB_OUTPUTXBAR6, HIC_BASESEL2 and HIC_NWE. |
| 49 | GPIO3 | bidirectional | General-purpose I/O 3 (default GPIO); alternates include EPWM2_B, OUTPUTXBAR2, PMBUSA_SCL (open-drain), SPIA_CLK, SCIA_RX, FSIRXA_D0, I2CB_SCL (open-drain), HIC_NOE, CANA_RX and HIC_D4. |
| 50 | GPIO2 | bidirectional | General-purpose I/O 2 (default GPIO); alternates include EPWM2_A, OUTPUTXBAR1, PMBUSA_SDA (open-drain), SPIA_SIMO, SCIA_TX, FSIRXA_D1, I2CB_SDA (open-drain), HIC_A1, CANA_TX and HIC_D9. |
| 51 | GPIO1 | bidirectional | General-purpose I/O 1 (default GPIO); alternates include EPWM1_B, I2CA_SCL (open-drain), SPIA_SOMI, CLB_OUTPUTXBAR7, HIC_A2, FSITXA_TDM_D1, and HIC_D10. |
| 52 | GPIO0 | bidirectional | General-purpose I/O 0 (default GPIO); alternates include EPWM1_A, I2CA_SDA (open-drain), SPIA_STE, FSIRXA_CLK, CLB_OUTPUTXBAR8 and HIC_BASESEL1. |
| 53 | GPIO40 | bidirectional | General-purpose I/O 40 (default GPIO); alternates include SPIB_SIMO, EPWM2_B, PMBUSA_SDA (open-drain), FSIRXA_D0, EQEP1_A, LINB_TX, HIC_NBE1 and HIC_D5. |
| 54 | GPIO23 | bidirectional | General-purpose I/O 23 (default GPIO); alternates include EQEP1_INDEX, SPIB_STE, LINA_RX, LINB_RX, HIC_A3, EPWM4_B and HIC_D11. |
| 55 | GPIO41 | bidirectional | General-purpose I/O 41 (default GPIO); alternates include EPWM2_A, PMBUSA_SCL (open-drain), FSIRXA_D1, EQEP1_B, LINB_RX, HIC_A4, SPIB_SOMI and HIC_D12. |
| 56 | GPIO22 | bidirectional | General-purpose I/O 22 (default GPIO); alternates include EQEP1_STROBE, SPIB_CLK, LINA_TX, CLB_OUTPUTXBAR1, LINB_TX, HIC_A5, EPWM4_A and HIC_D13. |
| 57 | GPIO7 | bidirectional | General-purpose I/O 7 (default GPIO); alternates include EPWM4_B, OUTPUTXBAR5, EQEP1_B, SPIB_SIMO, FSITXA_CLK, CLB_OUTPUTXBAR2, HIC_A6 and HIC_D14. |
| 58 | VSS | power_in | Digital ground pin. |
| 59 | VDD | power_in | 1.2 V digital logic supply pin. |
| 60 | VDDIO | power_in | 3.3 V digital I/O supply pin. |
| 61 | GPIO5 | bidirectional | General-purpose I/O 5 (default GPIO); alternates include EPWM3_B, OUTPUTXBAR3, CANA_RX, SPIA_STE, FSITXA_D1, CLB_OUTPUTXBAR5, HIC_A7, HIC_D4 and HIC_D15. |
| 62 | GPIO9 | bidirectional | General-purpose I/O 9 (default GPIO); alternates include EPWM5_B, OUTPUTXBAR6, EQEP1_INDEX, SCIA_RX, SPIA_CLK, FSITXA_D0, LINB_RX, HIC_BASESEL0, I2CB_SCL (open-drain) and HIC_NRDY. |
| 63 | GPIO10 | bidirectional | General-purpose I/O 10 (default GPIO); alternates include EPWM6_A, ADCSOCBO, EQEP1_A, SPIA_SOMI, I2CA_SDA (open-drain), FSITXA_CLK, LINB_TX, HIC_NWE and FSITXA_TDM_D0. |
| 64 | GPIO6 | bidirectional | General-purpose I/O 6 (default GPIO); alternates include EPWM4_A, OUTPUTXBAR4, SYNCOUT, EQEP1_A, SPIB_SOMI, FSITXA_D0, FSITXA_D1, HIC_NBE1, CLB_OUTPUTXBAR8 and HIC_D14. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |

## CAD (KiCad official)

- Symbol: `F280025CPMQR`
- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`
- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `f280025cpmqr-etched.step` / `f280025cpmqr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `f280025cpmqr.step` / `f280025cpmqr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tms320f280025c) (245 pp, sha256 `0723d8e3e09e1f8b`, retrieved 2026-10-12, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/f280025cpmqr-datasheet.pdf)