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F2800135PMR

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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F2800135PMR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

F2800135PMR from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO29 bidirectional General-purpose input/output 29 on the 3.3-V I/O domain; alternate mux functions are in the pin-multiplexing table, which is not fully present in the extracted pages.
2 A16/C16/GPIO28 bidirectional ADC-A input 16 and ADC-C input 16 shared with GPIO28; the GPIO is a full digital I/O only when the AGPIO is configured through AGPIOCTRL and GPxAMSEL.
3 XRSn input Active-low device reset input with internal pullup always active; boot starts only after XRSn is steadily high.
4 VDD power_in 1.2-V digital logic supply (1.14 V to 1.32 V recommended); place about 10 µF total decoupling near the VDD pins.
5 VSS power_in Digital ground; all VSS pins must be connected to board ground.
6 A6/C6/GPIO228 bidirectional ADC-A input 6 shared with GPIO228; also a CMPSS-1 low/high positive input (use AGPIO configuration for digital I/O).
7 C6/GPIO226 bidirectional ADC-C input 6 shared with GPIO226; also a CMPSS-3 positive input (AGPIO for digital I/O).
8 A3/C5/GPIO242 bidirectional ADC-A input 3 and ADC-C input 5 shared with GPIO242; also CMPSS-3 comparator inputs (AGPIO for digital I/O).
9 A2/C9/GPIO224 bidirectional ADC-A input 2 and ADC-C input 9 shared with GPIO224; also CMPSS-1 comparator inputs (AGPIO for digital I/O).
10 A15/C7 passive ADC-A input 15 and ADC-C input 7; also CMPSS-1/CMPSS-3 comparator inputs and AIO233, which is digital input only.
11 C4/A14 passive ADC-C input 4 and ADC-A input 14; also CMPSS-3 low/high positive input and AIO239, which is digital input only.
12 A11/C0 passive ADC-A input 11 and ADC-C input 0; also CMPSS-1 comparator inputs and AIO237, which is digital input only.
13 A5/C2 passive ADC-A input 5 and ADC-C input 2; also CMPSS-3 comparator inputs and AIO244, which is digital input only.
14 A1 passive ADC-A input 1; also CMPSS-1 low positive input 4 and AIO232, which is digital input only.
15 A0/C15/CMP1_DACL passive ADC-A input 0 and ADC-C input 15; CMPSS-1 low DAC output can be brought to this pin, and AIO231 is digital input only.
16 VREFHI input ADC high reference voltage (ratiometric, set by VREFHI/VREFLO); tie to VDDA if the ADC is not used.
17 VREFLO input ADC low reference voltage (ratiometric, set by VREFHI/VREFLO); tie to VSSA if the ADC is not used.
18 A12/C1 passive ADC-A input 12 and ADC-C input 1; CMPSS-2/CMPSS-4 combined analog group input and AIO238, which is digital input only.
19 A7/C3 passive ADC-A input 7 and ADC-C input 3; CMPSS-4 comparator inputs and AIO245, which is digital input only.
20 A8/C11 passive ADC-A input 8 and ADC-C input 11; CMPSS-2/CMPSS-4 comparator inputs and AIO241, which is digital input only.
21 VSSA power_in Analog ground; if a separate analog ground is not used, tie to VSS.
22 VDDA power_in 3.3-V analog supply (3.3 V to 3.63 V with internal BOR enabled); place a minimum 2.2-µF decoupling capacitor on the pin.
23 A4/C14 passive ADC-A input 4 and ADC-C input 14; CMPSS-2/CMPSS-4 comparator inputs and AIO225, which is digital input only.
24 C8/A9/GPIO227 bidirectional ADC-C input 8 and ADC-A input 9 shared with GPIO227; AGPIO digital I/O requires configuration.
25 A10/C10/GPIO230 bidirectional ADC-A input 10 and ADC-C input 10 shared with GPIO230; CMPSS-2 comparator input and AGPIO digital I/O when configured.
26 VSS power_in Digital ground; all VSS pins must be connected to board ground.
27 A17/C17/GPIO20 bidirectional ADC-A input 17 and ADC-C input 17 shared with GPIO20; AGPIO digital I/O requires configuration.
28 A18/C18/GPIO21 bidirectional ADC-A input 18 and ADC-C input 18 shared with GPIO21; AGPIO digital I/O requires configuration.
29 A19/C19/GPIO13 bidirectional ADC-A input 19 and ADC-C input 19 shared with GPIO13; AGPIO digital I/O requires configuration.
30 A20/C20/GPIO12 bidirectional ADC-A input 20 and ADC-C input 20 shared with GPIO12; AGPIO digital I/O requires configuration.
31 GPIO11 bidirectional General-purpose input/output 11 with muxed functions EPWM6_B, CANA_RX, OUTPUTXBAR7, EQEP1_B, SCIB_RX, SPIA_STE and SPIA_SIMO.
32 GPIO33 bidirectional General-purpose input/output 33; alternate functions are in the pin-multiplexing table, which is not fully present in the extracted pages.
33 GPIO16 bidirectional General-purpose input/output 16 with muxed functions SPIA_SIMO, OUTPUTXBAR7, EPWM5_A, SCIA_TX, EQEP1_STROBE and XCLKOUT.
34 GPIO17 bidirectional General-purpose input/output 17 with muxed functions SPIA_SOMI, OUTPUTXBAR8, EPWM5_B, SCIA_RX, EQEP1_INDEX, CANA_TX and EPWM6_A.
35 GPIO24 bidirectional General-purpose input/output 24 with muxed functions OUTPUTXBAR1, SPIA_STE, EPWM4_A, SPIA_SIMO, SCIA_TX and ERRORSTS (ERRORSTS requires an external pulldown).
36 TCK input JTAG test clock input with internal pullup active; leave unconnected or use a pullup resistor per the unused-pin table.
37 GPIO37/TDO tri_state JTAG test data output (default function); the pin is tri-stated when there is no JTAG activity, so an internal or external pullup is required to avoid a floating input.
38 TMS input JTAG test mode select input with internal pullup always active; an external pullup resistor is recommended.
39 GPIO35/TDI bidirectional JTAG test data input (default function); internal pullup is disabled by default, so enable it or add an external pullup if used as TDI.
40 GPIO32 bidirectional General-purpose input/output 32; alternate functions are in the pin-multiplexing table, which is not fully present in the extracted pages.
41 GPIO18/X2 bidirectional General-purpose input/output 18 (with SPIA_CLK, SCIB_TX, CANA_RX, EPWM6_A, I2CA_SCL, XCLKOUT) or crystal oscillator output X2 in the alternate function.
42 GPIO19/X1 bidirectional General-purpose input/output 19 or crystal oscillator/single-ended clock input X1; initialization software must configure this pin before enabling the crystal oscillator.
43 VDDIO power_in 3.3-V digital I/O supply (3.3 V to 3.63 V); place a minimum 0.1-µF decoupling capacitor on the pin.
44 VDD power_in 1.2-V digital logic supply (1.14 V to 1.32 V recommended); place decoupling near the pin as part of the approximately 10 µF total VDD capacitance.
45 VSS power_in Digital ground; all VSS pins must be connected to board ground.
46 GPIO39 bidirectional General-purpose input/output 39; this pin is near the power management module, so avoid negative noise on it (VREGENZ function applies only to the 64 VPM variant).
47 GPIO8 bidirectional General-purpose input/output 8 with muxed functions EPWM5_A, ADCSOCAO, EQEP1_STROBE, SCIA_TX, SPIA_SIMO and I2CA_SCL (open-drain); near the PMM, so avoid negative noise.
48 GPIO4 bidirectional General-purpose input/output 4; this pin is near the power management module, so avoid negative noise on it.
49 GPIO3 bidirectional General-purpose input/output 3; this pin is near the power management module, so avoid negative noise on it.
50 GPIO2 bidirectional General-purpose input/output 2; alternate functions are in the pin-multiplexing table, which is not fully present in the extracted pages.
51 GPIO1 bidirectional General-purpose input/output 1; alternate functions are in the pin-multiplexing table, which is not fully present in the extracted pages.
52 GPIO0 bidirectional General-purpose input/output 0; alternate functions are in the pin-multiplexing table, which is not fully present in the extracted pages.
53 GPIO40 bidirectional General-purpose input/output 40; alternate functions are in the pin-multiplexing table, which is not fully present in the extracted pages.
54 GPIO23 bidirectional General-purpose input/output 23 with muxed functions EQEP1_INDEX, SCIB_RX, SCIC_RX and EPWM4_B.
55 GPIO41 bidirectional General-purpose input/output 41; alternate functions are in the pin-multiplexing table, which is not fully present in the extracted pages.
56 GPIO22 bidirectional General-purpose input/output 22 with muxed functions EQEP1_STROBE, SCIB_TX, SCIC_TX and EPWM4_A.
57 GPIO7 bidirectional General-purpose input/output 7 with muxed functions EPWM4_B, EPWM2_A, OUTPUTXBAR5, EQEP1_B, SPIA_SIMO, SCIA_TX and CANA_TX.
58 VSS power_in Digital ground; all VSS pins must be connected to board ground.
59 VDD power_in 1.2-V digital logic supply (1.14 V to 1.32 V recommended); place decoupling near the pin as part of the approximately 10 µF total VDD capacitance.
60 VDDIO power_in 3.3-V digital I/O supply (3.3 V to 3.63 V); place a minimum 0.1-µF decoupling capacitor on the pin.
61 GPIO5 bidirectional General-purpose input/output 5; alternate functions are in the pin-multiplexing table, which is not fully present in the extracted pages.
62 GPIO9 bidirectional General-purpose input/output 9 with muxed functions EPWM5_B, SCIB_TX, OUTPUTXBAR6, EQEP1_INDEX, SCIA_RX, SPIA_CLK and I2CB_SCL (open-drain).
63 GPIO10 bidirectional General-purpose input/output 10 with muxed functions EPWM6_A, ADCSOCBO, EQEP1_A, SCIB_TX, SPIA_SOMI and I2CA_SDA (open-drain).
64 GPIO6 bidirectional General-purpose input/output 6 with muxed functions EPWM4_A, OUTPUTXBAR4, SYNCOUT, EQEP1_A and EPWM2_A.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

CAD (KiCad official)

  • Symbol: F2800135PMR
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: f2800135pmr-etched.step / f2800135pmr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); f2800135pmr.step / f2800135pmr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (219 pp, sha256 778bb72dfd60fad1, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF