# EZJZ0V500AA

**PANASONIC** · Varistors · 0402

EZJZ0V500AA from PANASONIC, in a 0402. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1 | passive | Terminal 1 of an unpolarised resistor; either orientation. |
| 2 | 2 | passive | Terminal 2 of an unpolarised resistor; either orientation. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | PANASONIC |
| Package | 0402 |
| Category | Circuit Protection |
| Pins | 2 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Varistor voltage change at soldering heat (resistance to soldering heat) | ΔVc/Vc | -10 |  | 10 | % | After resistance to soldering heat test (270 °C 3 s / 260 °C 10 s), left 24±2 h | 8 |
| Varistor voltage change at temperature cycling | ΔVc/Vc | -10 |  | 10 | % | After 5 temperature cycles (max. to min. operating temp), left 24±2 h | 8 |
| Varistor voltage change at biased humidity | ΔVc/Vc | -10 |  | 10 | % | After 40±2 °C, 90 to 95 %RH, max. allowable voltage applied, 500 h, left 24±2 h | 8 |
| Varistor voltage change at high temperature exposure | ΔVc/Vc | -10 |  | 10 | % | After max. operating temp ±3 °C with max. allowable voltage applied, 500 h, left 24±2 h | 8 |
| Maximum ESD (IEC61000-4-2) |  |  |  | 8 | kV | Contact discharge, IEC61000-4-2, 10 times (5 each polarity), per 0402 group row | 2 |
| Operating temperature range |  | -40 |  | 85 | °C | Operating temperature range | 2 |
| Maximum allowable voltage DC |  |  |  | 5 | V | Maximum DC voltage that can be applied continuously within the operating temperature range | 2 |
| Capacitance |  |  | 2.1 | 3 | pF | at 1 MHz (printed as 3 pF max. [2.1 pF typ.]) | 2 |
| Nominal varistor voltage |  |  | 50 |  | V | at 1 mA DC | 2 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC |  | PC, PDA USB2.0, IEEE1394, LAN1000BASE | 2 |

## CAD (KiCad official)

- Symbol: `EZJZ0V500AA`
- Footprint: `Resistor_SMD:R_0402_1005Metric`
- 3D model: 0402 (KiCad packages3D, STEP)
- 3D model files: `ezjz0v500aa-etched.step` / `ezjz0v500aa-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ezjz0v500aa.step` / `ezjz0v500aa.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [PANASONIC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588930734353993728) (8 pp, sha256 `cfca3c660a7de375`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins`, primary `two-terminal convention` (convention), consensus `off` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ezjz0v500aa-datasheet.pdf)