# EZAEG3W11AV

**PANASONIC** · Varistors · 0603

EZAEG3W11AV from PANASONIC, in a 0603. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1 | passive | Terminal electrode of the bidirectional ESD suppressor, connected to the protected line, with 50 V DC max rated voltage, 0.10 pF capacitance and 1000 V max peak voltage. |
| 2 | 2 | passive | Second terminal electrode of the bidirectional ESD suppressor, connected to ground or the opposite side of the protected path, interchangeable with the other terminal (50 V DC rated). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | PANASONIC |
| Package | 0603 |
| Category | Circuit Protection |
| Pins | 2 |

## CAD (KiCad official)

- Symbol: `EZAEG3W11AV`
- Footprint: `Resistor_SMD:R_0603_1608Metric`
- 3D model: 0603 (KiCad packages3D, STEP)
- 3D model files: `ezaeg3w11av-etched.step` / `ezaeg3w11av-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ezaeg3w11av.step` / `ezaeg3w11av.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [PANASONIC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588905470249062400) (5 pp, sha256 `eb4c7fb191f8a196`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ezaeg3w11av-datasheet.pdf)