# EX9610PD

**Existar** · Synchronous Rectifier Controllers · SOP-8

EX9610PD from Existar, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No connection. Floating pin, no electrical function. Leave open on the PCB. |
| 2 | VDD | power_in | Chip supply pin. Fed from the internal 150V JFET self-supply through an LDO regulated to 7.7V typ (7.5-7.9V, with CVDD=1uF, HV=40V). Startup threshold 7.4V, UVLO 5.3V, clamp 8.3V. Requires a 1uF ceramic cap to S (GND) placed close to the pin. |
| 3 | S | power_in | Source of the internal power MOSFET and ground reference for the control die. Pins 3 and 4 are internally tied - both must be connected to the low-side (output-side) net with a low-impedance path. |
| 4 | S | power_in | Source of the internal power MOSFET and ground reference for the control die. Internally tied to pin 3. |
| 5 | D | power_in | Drain of the internal 100V / 15mΩ SGT MOSFET and high-voltage sense / self-supply input. Pins 5, 6, 7, 8 are internally tied - parallel them and route close to the transformer secondary to minimise conduction and switching-node loss. Absolute max −0.3 to 100V; recommended operating <100V. |
| 6 | D | power_in | Drain of the internal power MOSFET / HV sense. Internally tied to pins 5, 7, 8. |
| 7 | D | power_in | Drain of the internal power MOSFET / HV sense. Internally tied to pins 5, 6, 8. |
| 8 | D | power_in | Drain of the internal power MOSFET / HV sense. Internally tied to pins 5, 6, 7. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Existar |
| Package | SOP-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |

## Ordering variants

Same part, different packaging or reel option.

- `EX9610PD`

## CAD (KiCad official)

- Symbol: `EX9610PD`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `ex9610pd-etched.step` / `ex9610pd-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ex9610pd.step` / `ex9610pd.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Existar datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603515453272563712) (8 pp, sha256 `9ea1cf2d8026533e`, retrieved 2026-08-17, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ex9610pd-datasheet.pdf)