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ETP01-1621RL
Public Made by Adomby adom
STMicroelectronics Semiconductor Discharge Tubes (TSS), SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ETP01-1621RL
STMicroelectronics · Semiconductor Discharge Tubes (TSS) · SOIC-8
ETP01-1621RL from STMicroelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | T1 | passive | Protected line terminal T1 (I/O) of the Trisil surge arrestor, internally tied to pin 8, with 13 pF max capacitance to GND at 0 V. |
| 2 | GND | power_in | Ground reference terminal of the surge arrestor, common with pins 3, 6 and 7. |
| 3 | GND | power_in | Ground reference terminal of the surge arrestor, common with pins 2, 6 and 7. |
| 4 | T2 | passive | Protected line terminal T2 (I/O) of the Trisil surge arrestor, internally tied to pin 5, with 13 pF max capacitance to GND at 0 V. |
| 5 | T2 | passive | Protected line terminal T2 (I/O) of the Trisil surge arrestor, internally tied to pin 4, with 13 pF max capacitance to GND at 0 V. |
| 6 | GND | power_in | Ground reference terminal of the surge arrestor, common with pins 2, 3 and 7. |
| 7 | GND | power_in | Ground reference terminal of the surge arrestor, common with pins 2, 3 and 6. |
| 8 | T1 | passive | Protected line terminal T1 (I/O) of the Trisil surge arrestor, internally tied to pin 1, with 13 pF max capacitance to GND at 0 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SOIC-8 |
| Category | Circuit Protection |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
ETP01-1621RL - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
etp01-1621rl-etched.step/etp01-1621rl-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);etp01-1621rl.step/etp01-1621rl.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (7 pp, sha256
8badb08d5ec31c9b, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ETP01-1621RL
**STMicroelectronics** · Semiconductor Discharge Tubes (TSS) · SOIC-8
ETP01-1621RL from STMicroelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | T1 | passive | Protected line terminal T1 (I/O) of the Trisil surge arrestor, internally tied to pin 8, with 13 pF max capacitance to GND at 0 V. |
| 2 | GND | power_in | Ground reference terminal of the surge arrestor, common with pins 3, 6 and 7. |
| 3 | GND | power_in | Ground reference terminal of the surge arrestor, common with pins 2, 6 and 7. |
| 4 | T2 | passive | Protected line terminal T2 (I/O) of the Trisil surge arrestor, internally tied to pin 5, with 13 pF max capacitance to GND at 0 V. |
| 5 | T2 | passive | Protected line terminal T2 (I/O) of the Trisil surge arrestor, internally tied to pin 4, with 13 pF max capacitance to GND at 0 V. |
| 6 | GND | power_in | Ground reference terminal of the surge arrestor, common with pins 2, 3 and 7. |
| 7 | GND | power_in | Ground reference terminal of the surge arrestor, common with pins 2, 3 and 6. |
| 8 | T1 | passive | Protected line terminal T1 (I/O) of the Trisil surge arrestor, internally tied to pin 1, with 13 pF max capacitance to GND at 0 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SOIC-8 |
| Category | Circuit Protection |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `ETP01-1621RL`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `etp01-1621rl-etched.step` / `etp01-1621rl-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `etp01-1621rl.step` / `etp01-1621rl.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588912943266746368) (7 pp, sha256 `8badb08d5ec31c9b`, retrieved 2026-10-11, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/etp01-1621rl-datasheet.pdf)