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ETA5050V12S2F

Public Made by Adom

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ETA(钰泰) Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ETA5050V12S2F

ETA(钰泰) · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

ETA5050V12S2F from ETA(钰泰), in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VIN power_in Input supply pin; the datasheet gives an input voltage range of 1.6 V to 6.0 V and an absolute maximum of -0.3 V to 6 V for VIN.
2 GND power_in Ground pin.
3 EN input Enable pin: drive high to enable the IC and low to disable it, with logic low at most 0.4 V and logic high at least 1.4 V for 1.8 V ≤ VIN ≤ 6 V; it may be connected to the input if not used.
4 NC unconnected Not connected.
5 VOUT power_out Regulator output, fixed at 1.2 V for the V12 part, with a 500 mA continuous output current if not limited by package heat dissipation and dropout.

Key specifications

Parameter Value
Manufacturer ETA(钰泰)
Package SOT-23-5
Category Power Management (PMIC)
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Voltage Range VIN 1.6 6 V 2
Output Voltage Range 1 3.95 V Available in 50mV steps 2
Vout Voltage accuracy -2 2 % IOUT =30mA 2
Dropout Voltage 850 1000 mV IOUT = 300mA, VOUT = 1.2V 2
Ground Current 37 60 µA No Load 2
Shutdown Current 0 1 µA VEN = 0V 2
EN pin input Logic Low 0.4 V 1.8V ≤ VIN ≤6V 2
EN pin input Logic High 1.4 V 1.8V ≤ VIN ≤ 6V 2
Line Regulation 0.12 %/V VOUT + 1V ≤ VIN ≤ 6V 2
Load Regulation 20 mV 0µA ≤ IOUT ≤ 200 mA 2
Output Current Limit 500 mA VOUT = 95% 2
Output Foldback Current Limit 250 mA VOUT = 0V 2
Continuous Output Current 500 mA If not limited by heat dissipation of package and dropout 2
Power Supply Rejection Ratio PSRR 73 dB Freq = 100Hz, IOUT = 30mA 2
Power Supply Rejection Ratio PSRR 70 dB Freq = 1kHz, IOUT = 30mA 2
Start-up time 50 µs 2
Input current at EN pin 1 µA VEN=3V 3
Thermal Shutdown 150 °C Rising, Hysteresis =30° C 3
Output Noise Voltage 50 µVRMS BW=10Hz to 100KHz 3
VIN, EN, VOUT Voltage VIN, EN, VOUT -0.3 6 V 2
Junction Temperature 150 °C 2
Storage Temperature Range -55 150 °C 2
ESD HBM (Human Body Mode) 2 KV Human Body Model 2
ESD CDM (Charge Device Mode) 1 KV Charge Device Mode 2
Ambient Temperature Range -40 85 C 2
Junction Temperature Range -40 125 C 2
Thermal Resistance junction-to-ambient (SOT23-5) JA 163 °C/W SOT23-5 2
Thermal Resistance junction-to-case (SOT23-5) JC 55 °C/W SOT23-5 2

CAD (KiCad official)

  • Symbol: ETA5050V12S2F
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: eta5050v12s2f-etched.step / eta5050v12s2f-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); eta5050v12s2f.step / eta5050v12s2f.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ETA(钰泰) datasheet (10 pp, sha256 30a26535df70e89b, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF