component
ESP32-S3RH2
Public Made by Adomby adom
Espressif Systems RF and Wireless, 56-VFQFN Exposed Pad. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Made with kicad-footprint-generator 10.0 · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 1d ago |
| viewers | 1d ago |
| esp32-s3rh2-etched.glb | 1d ago |
| esp32-s3rh2-etched.step | 1d ago |
| esp32-s3rh2-hero.glb | 1d ago |
| esp32-s3rh2-hero.overlay.json | 1d ago |
| esp32-s3rh2.glb | 1d ago |
| esp32-s3rh2.kicad_mod | 1d ago |
| esp32-s3rh2.kicad_sym | 1d ago |
| esp32-s3rh2.lbr | 1d ago |
| esp32-s3rh2.step | 1d ago |
| package.json | 1d ago |
| page.json | 1d ago |
| README.md | 1d ago |
ESP32-S3RH2
Espressif Systems · RF and Wireless · 56-VFQFN Exposed Pad
ESP32-S3RH2 from Espressif Systems, in a 56-VFQFN Exposed Pad. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LNA_IN | bidirectional | RF Low Noise Amplifier input/output signal for the 2.4 GHz radio. |
| 2 | VDD3P3 | power_in | Input supply for the analog power domain. |
| 3 | VDD3P3 | power_in | Input supply for the analog power domain. |
| 4 | CHIP_PU | input | High enables the chip and low powers it down; the pin must not be left floating. |
| 5 | GPIO0 | bidirectional | Powered by VDD3P3_RTC with a weak pull-up at reset; it is a strapping pin for chip boot mode. |
| 6 | GPIO1 | bidirectional | Powered by VDD3P3_RTC; also provides RTC_GPIO1, TOUCH1 and ADC1_CH0 functions. |
| 7 | GPIO2 | bidirectional | Powered by VDD3P3_RTC; also provides RTC_GPIO2, TOUCH2 and ADC1_CH1 functions. |
| 8 | GPIO3 | bidirectional | Powered by VDD3P3_RTC; floating at reset and used as a strapping pin for the JTAG signal source. |
| 9 | GPIO4 | bidirectional | Powered by VDD3P3_RTC; also provides RTC_GPIO4, TOUCH4 and ADC1_CH3 functions. |
| 10 | GPIO5 | bidirectional | Powered by VDD3P3_RTC; also provides RTC_GPIO5, TOUCH5 and ADC1_CH4 functions. |
| 11 | GPIO6 | bidirectional | Powered by VDD3P3_RTC; also provides RTC_GPIO6, TOUCH6 and ADC1_CH5 functions. |
| 12 | GPIO7 | bidirectional | Powered by VDD3P3_RTC; also provides RTC_GPIO7, TOUCH7 and ADC1_CH6 functions. |
| 13 | GPIO8 | bidirectional | Powered by VDD3P3_RTC; also provides RTC_GPIO8, TOUCH8, ADC1_CH7 and SUBSPICS1 functions. |
| 14 | GPIO9 | bidirectional | Powered by VDD3P3_RTC; also provides RTC_GPIO9, TOUCH9, ADC1_CH8 and SUBSPIHD/FSPIHD functions. |
| 15 | GPIO10 | bidirectional | Powered by VDD3P3_RTC; also provides RTC_GPIO10, TOUCH10, ADC1_CH9 and SUBSPICS0/FSPICS0 functions. |
| 16 | GPIO11 | bidirectional | Powered by VDD3P3_RTC; also provides RTC_GPIO11, TOUCH11, ADC2_CH0 and SUBSPID/FSPID functions. |
| 17 | GPIO12 | bidirectional | Powered by VDD3P3_RTC; also provides RTC_GPIO12, TOUCH12, ADC2_CH1 and SUBSPICLK/FSPICLK functions. |
| 18 | GPIO13 | bidirectional | Powered by VDD3P3_RTC; also provides RTC_GPIO13, TOUCH13, ADC2_CH2 and SUBSPIQ/FSPIQ functions. |
| 19 | GPIO14 | bidirectional | Powered by VDD3P3_RTC; also provides RTC_GPIO14, TOUCH14, ADC2_CH3 and SUBSPIWP/FSPIWP functions. |
| 20 | VDD3P3_RTC | power_in | Input supply for the RTC and part of the digital power domains, powering the RTC IO pins. |
| 21 | XTAL_32K_P | bidirectional | 32 kHz external clock input/output connected to the chip oscillator; also provides RTC_GPIO15 and ADC2_CH4. |
| 22 | XTAL_32K_N | bidirectional | Negative terminal of the 32 kHz external clock input/output; also provides RTC_GPIO16 and ADC2_CH5. |
| 23 | GPIO17 | bidirectional | Powered by VDD3P3_RTC with a default drive strength of 10 mA; also provides RTC_GPIO17 and ADC2_CH6. |
| 24 | GPIO18 | bidirectional | Powered by VDD3P3_RTC with a default drive strength of 10 mA; also provides RTC_GPIO18 and ADC2_CH7. |
| 25 | GPIO19 | bidirectional | Powered by VDD3P3_RTC with a default drive strength of 40 mA; defaults to the USB_D- function of the USB Serial/JTAG controller. |
| 26 | GPIO20 | bidirectional | Powered by VDD3P3_RTC with a default drive strength of 40 mA; defaults to the USB_D+ function with the USB pull-up enabled. |
| 27 | GPIO21 | bidirectional | Powered by VDD3P3_RTC; general-purpose IO that also provides RTC_GPIO21. |
| 28 | SPICS1 | bidirectional | Powered by VDD_SPI with a weak pull-up at reset; connects to the in-package PSRAM chip enable (CE#). |
| 29 | VDD_SPI | power_in | Power pin acting as an input from the backup power line for in-package memory or as an output supplying in-package and off-package flash/PSRAM SPI IO. |
| 30 | SPIHD | bidirectional | Powered by VDD_SPI with a weak pull-up at reset; hold signal for the flash/PSRAM SPI bus (HOLD# / SIO3). |
| 31 | SPIWP | bidirectional | Powered by VDD_SPI with a weak pull-up at reset; write-protect signal for the flash/PSRAM SPI bus (WP# / SIO2). |
| 32 | SPICS0 | bidirectional | Powered by VDD_SPI with a weak pull-up at reset; chip select for the in-package flash (CS0). |
| 33 | SPICLK | bidirectional | Powered by VDD_SPI with a weak pull-up at reset; clock output for the flash/PSRAM SPI bus. |
| 34 | SPIQ | bidirectional | Powered by VDD_SPI with a weak pull-up at reset; data line for the flash/PSRAM SPI bus (DO / SO/SIO1). |
| 35 | SPID | bidirectional | Powered by VDD_SPI with a weak pull-up at reset; data line for the flash/PSRAM SPI bus (DI / SI/SIO0). |
| 36 | SPICLK_N | bidirectional | Negative differential SPI clock powered by VDD_SPI or VDD3P3_CPU, also available as GPIO48. |
| 37 | SPICLK_P | bidirectional | Positive differential SPI clock powered by VDD_SPI or VDD3P3_CPU, also available as GPIO47. |
| 38 | GPIO33 | bidirectional | Powered by VDD_SPI or VDD3P3_CPU; carries flash/PSRAM data line DQ4 in 8-line SPI mode. |
| 39 | GPIO34 | bidirectional | Powered by VDD_SPI or VDD3P3_CPU; carries flash/PSRAM data line DQ5 in 8-line SPI mode. |
| 40 | GPIO35 | bidirectional | Powered by VDD_SPI or VDD3P3_CPU; carries flash/PSRAM data line DQ6 in 8-line SPI mode. |
| 41 | GPIO36 | bidirectional | Powered by VDD_SPI or VDD3P3_CPU; carries flash/PSRAM data line DQ7 in 8-line SPI mode. |
| 42 | GPIO37 | bidirectional | Powered by VDD_SPI or VDD3P3_CPU; carries the DQS/DM strobe in 8-line SPI mode. |
| 43 | GPIO38 | bidirectional | Powered by VDD3P3_CPU with a default drive strength of 20 mA; general-purpose IO with FSPIWP and SUBSPIWP functions. |
| 44 | MTCK | bidirectional | Powered by VDD3P3_CPU; JTAG test clock, also available as GPIO39. |
| 45 | MTDO | bidirectional | Powered by VDD3P3_CPU; JTAG test data out, also available as GPIO40. |
| 46 | VDD3P3_CPU | power_in | Input supply for the digital power domain that powers the digital IO pins. |
| 47 | MTDI | bidirectional | Powered by VDD3P3_CPU; JTAG test data in, also available as GPIO41. |
| 48 | MTMS | bidirectional | Powered by VDD3P3_CPU; JTAG test mode select, also available as GPIO42. |
| 49 | U0TXD | bidirectional | Powered by VDD3P3_CPU with a weak pull-up at reset; UART0 transmit data, also available as GPIO43. |
| 50 | U0RXD | bidirectional | Powered by VDD3P3_CPU with a weak pull-up at reset; UART0 receive data, also available as GPIO44. |
| 51 | GPIO45 | bidirectional | Powered by VDD3P3_CPU with a weak pull-down at reset; strapping pin that sets the VDD_SPI voltage. |
| 52 | GPIO46 | bidirectional | Powered by VDD3P3_CPU with a weak pull-down at reset; strapping pin that sets the chip boot mode and ROM message printing. |
| 53 | XTAL_N | passive | Negative terminal of the external clock input/output connected to the chip crystal or oscillator. |
| 54 | XTAL_P | passive | Positive terminal of the external clock input/output connected to the chip crystal or oscillator. |
| 55 | VDDA | power_in | Input supply for the analog power domain. |
| 56 | VDDA | power_in | Input supply for the analog power domain. |
| 57 | GND | power_in | External ground connection (exposed pad). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Espressif Systems |
| Package | 56-VFQFN Exposed Pad |
| Category | RF and Wireless |
| Pins | 57 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Allowed input voltage (input power pins) | -0.3 | 3.6 | V | 64 | |||
| Cumulative IO output current | Ioutput | 1500 | mA | 64 | |||
| Storage temperature | TSTORE | -40 | 150 | °C | 64 | ||
| Recommended input voltage (VDDA, VDD3P3) | VDDA, VDD3P3 | 3 | 3.3 | 3.6 | V | 64 | |
| Recommended input voltage (VDD3P3_RTC) | VDD3P3_RTC | 3 | 3.3 | 3.6 | V | 64 | |
| Recommended input voltage (VDD3P3_CPU) | VDD3P3_CPU | 3 | 3.3 | 3.6 | V | 64 | |
| Recommended input voltage (VDD_SPI as input) | VDD_SPI | 1.8 | 3.3 | 3.6 | V | VDD_SPI as input | 64 |
| Cumulative input current | IVDD | 0.5 | A | 64 | |||
| Power-up time reserved for power rails to stabilize before CHIP_PU is high | tSTBL | 50 | µs | VDDA, VDD3P3, VDD3P3_RTC, VDD3P3_CPU stabilize before CHIP_PU is pulled high | 30 | ||
| Reset time with CHIP_PU below VIL_nRST | tRST | 50 | µs | CHIP_PU stays below VIL_nRST to reset the chip | 30 | ||
| Pin capacitance | CIN | 2 | pF | 65 | |||
| High-level input current | IIH | 50 | nA | 65 | |||
| Low-level input current | IIL | 50 | nA | 65 | |||
| High-level source current | IOH | 40 | mA | VDD = 3.3 V, VOH >= 2.64 V, PAD_DRIVER = 3 | 65 | ||
| Low-level sink current | IOL | 28 | mA | VDD = 3.3 V, VOL = 0.495 V, PAD_DRIVER = 3 | 65 | ||
| Internal weak pull-up resistor | RPU | 45 | kΩ | 65 | |||
| Internal weak pull-down resistor | RPD | 45 | kΩ | 65 | |||
| VDD_SPI internal resistance (powered by VDD3P3_RTC via RSPI) | RSPI | 14 | Ω | VDD_SPI powered by VDD3P3_RTC via RSPI for 3.3 V flash/PSRAM | 65 | ||
| VDD_SPI output current (Flash Voltage Regulator, 1.8 V flash/PSRAM) | ISPI | 40 | mA | VDD_SPI powered by Flash Voltage Regulator for 1.8 V flash/PSRAM | 65 | ||
| Differential nonlinearity | DNL | -4 | 4 | LSB | external 100 nF capacitor on ADC, 25 °C, Wi-Fi disabled | 66 | |
| Integral nonlinearity | INL | -8 | 8 | LSB | external 100 nF capacitor on ADC, 25 °C, Wi-Fi disabled | 66 | |
| ADC sampling rate | 100 | kSPS | 66 | ||||
| ADC total error (ATTEN0) | -5 | 5 | mV | ATTEN0, effective measurement range of 0 ~ 850 | 66 | ||
| ADC total error (ATTEN1) | -6 | 6 | mV | ATTEN1, effective measurement range of 0 ~ 1100 | 66 | ||
| ADC total error (ATTEN2) | -10 | 10 | mV | ATTEN2, effective measurement range of 0 ~ 1600 | 66 | ||
| ADC total error (ATTEN3) | -50 | 50 | mV | ATTEN3, effective measurement range of 0 ~ 2900 | 66 | ||
| RF power control range (Bluetooth LE 1 Mbps) | -24 | 0 | 20 | dBm | 73 | ||
| Gain control step (Bluetooth LE 1 Mbps) | 3 | dB | 73 |
CAD (KiCad official)
- Symbol:
ESP32-S3RH2 - Footprint:
Package_DFN_QFN:QFN-56-1EP_7x7mm_P0.4mm_EP5.6x5.6mm - 3D model: 56-VFQFN Exposed Pad (KiCad packages3D, STEP)
- 3D model files:
esp32-s3rh2-etched.step/esp32-s3rh2-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);esp32-s3rh2.step/esp32-s3rh2.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Espressif Systems datasheet (87 pp, sha256
2d5a7cb7fd559d8d, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).