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ESP32-S3R8
Public Made by Adomby adom
Espressif Systems RF Transceiver ICs, QFN-56(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownESP32-S3R8
Espressif Systems · RF Transceiver ICs · QFN-56(7x7)
ESP32-S3R8 from Espressif Systems, in a QFN-56(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LNA_IN | bidirectional | Low-noise amplifier input/output for 2.4 GHz RF signals, receives and transmits RF with impedance-controlled interface for antenna routing |
| 2 | VDD3P3 | power_in | Analog power domain supply input, recommended voltage 3.0 to 3.6 V |
| 3 | VDD3P3 | power_in | Analog power domain supply input, recommended voltage 3.0 to 3.6 V |
| 4 | CHIP_PU | input | Chip power-up enable input: high level enables chip operation, low level powers down chip; must not be left floating |
| 5 | GPIO0 | bidirectional | General-purpose digital I/O pin with RTC_GPIO0 and SAR I2C functions, internal weak pull-up enabled at reset, strapping pin for SPI boot mode |
| 6 | GPIO1 | bidirectional | General-purpose digital I/O pin with RTC_GPIO1, TOUCH1, and ADC1_CH0 analog functions, input enabled at reset |
| 7 | GPIO2 | bidirectional | General-purpose digital I/O pin with RTC_GPIO2, TOUCH2, and ADC1_CH1 analog functions, input enabled at reset |
| 8 | GPIO3 | bidirectional | General-purpose digital I/O pin with RTC_GPIO3, TOUCH3, and ADC1_CH2 analog functions; strapping pin for JTAG signal source selection, input enabled at reset |
| 9 | GPIO4 | bidirectional | General-purpose digital I/O pin with RTC_GPIO4, TOUCH4, and ADC1_CH3 analog functions |
| 10 | GPIO5 | bidirectional | General-purpose digital I/O pin with RTC_GPIO5, TOUCH5, and ADC1_CH4 analog functions |
| 11 | GPIO6 | bidirectional | General-purpose digital I/O pin with RTC_GPIO6, TOUCH6, and ADC1_CH5 analog functions |
| 12 | GPIO7 | bidirectional | General-purpose digital I/O pin with RTC_GPIO7, TOUCH7, and ADC1_CH6 analog functions |
| 13 | GPIO8 | bidirectional | General-purpose digital I/O pin with RTC_GPIO8, TOUCH8, and ADC1_CH7 analog functions; can be routed as SUBSPI CS1 output |
| 14 | GPIO9 | bidirectional | General-purpose digital I/O pin with RTC_GPIO9, TOUCH9, and ADC1_CH8 analog functions; can be routed as SUBSPI HD or FSPI HD, input enabled at reset |
| 15 | GPIO10 | bidirectional | General-purpose digital I/O pin with RTC_GPIO10, TOUCH10, and ADC1_CH9 analog functions; can be routed as FSPI IO4 or SUBSPI CS0, input enabled at reset |
| 16 | GPIO11 | bidirectional | General-purpose digital I/O pin with RTC_GPIO11, TOUCH11, and ADC2_CH0 analog functions; can be routed as FSPI IO5 or SUBSPI D, input enabled at reset |
| 17 | GPIO12 | bidirectional | General-purpose digital I/O pin with RTC_GPIO12, TOUCH12, and ADC2_CH1 analog functions; can be routed as FSPI IO6 or SUBSPI CLK, input enabled at reset |
| 18 | GPIO13 | bidirectional | General-purpose digital I/O pin with RTC_GPIO13, TOUCH13, and ADC2_CH2 analog functions; can be routed as FSPI IO7 or SUBSPI Q, input enabled at reset |
| 19 | GPIO14 | bidirectional | General-purpose digital I/O pin with RTC_GPIO14, TOUCH14, and ADC2_CH3 analog functions; can be routed as FSPI DQS or SUBSPI WP, input enabled at reset |
| 20 | VDD3P3_RTC | power_in | RTC and digital power domain supply input, recommended voltage 3.0 to 3.6 V, powers RTC module and GPIO27-GPIO14 |
| 21 | XTAL_32K_P | passive | External 32 kHz crystal oscillator positive terminal for RTC slow clock; RTC_GPIO15 and ADC2_CH4 analog function available |
| 22 | XTAL_32K_N | passive | External 32 kHz crystal oscillator negative terminal for RTC slow clock; RTC_GPIO16 and ADC2_CH5 analog function available |
| 23 | GPIO17 | bidirectional | General-purpose digital I/O pin with RTC_GPIO17 and ADC2_CH6 analog functions, input enabled at reset |
| 24 | GPIO18 | bidirectional | General-purpose digital I/O pin with RTC_GPIO18 and ADC2_CH7 analog functions; can output CLK_OUT3, input enabled at reset, exhibits 60 µs low-level glitch at power-up |
| 25 | GPIO19 | bidirectional | General-purpose digital I/O pin with RTC_GPIO19, USB_D- and ADC2_CH8 analog functions; can output CLK_OUT2, exhibits two 60 µs high-level glitches (3.2 ms total) at power-up |
| 26 | GPIO20 | bidirectional | General-purpose digital I/O pin with RTC_GPIO20, USB_D+ and ADC2_CH9 analog functions; internal weak pull-up enabled by default for USB Serial/JTAG; can output CLK_OUT1; exhibits 60 µs pull-down and high-level glitches (2 ms total) at power-up |
| 27 | GPIO21 | bidirectional | General-purpose digital I/O pin with RTC_GPIO21 function |
| 28 | SPICS1 | bidirectional | SPI chip select 1 output for in-package PSRAM; GPIO26 routing via GPIO matrix available; internal weak pull-up enabled at reset |
| 29 | VDD_SPI | power_in | In-package memory and SPI flash/PSRAM supply input/output (backup power line), voltage 1.8 to 3.6 V depending on variant and configuration |
| 30 | SPIHD | bidirectional | SPI hold signal for flash/PSRAM in quad and octal SPI modes; GPIO27 routing via GPIO matrix available; internal weak pull-up enabled at reset |
| 31 | SPIWP | bidirectional | SPI write protect signal for flash/PSRAM in quad and octal SPI modes; GPIO28 routing via GPIO matrix available; internal weak pull-up enabled at reset |
| 32 | SPICS0 | bidirectional | SPI chip select 0 output for in-package flash; GPIO29 routing via GPIO matrix available; internal weak pull-up enabled at reset |
| 33 | SPICLK | bidirectional | SPI clock output for flash/PSRAM in SPI modes; GPIO30 routing via GPIO matrix available; internal weak pull-up enabled at reset |
| 34 | SPIQ | bidirectional | SPI Q data line (SO/SIO1) for flash/PSRAM in quad and octal SPI modes; GPIO31 routing via GPIO matrix available; internal weak pull-up enabled at reset |
| 35 | SPID | bidirectional | SPI D data line (SI/SIO0) for flash/PSRAM in quad and octal SPI modes; GPIO32 routing via GPIO matrix available; internal weak pull-up enabled at reset |
| 36 | SPICLK_N | tri_state | Differential SPI clock negative for 8-line octal SPI mode (DQ3); GPIO48 routing via GPIO matrix available; powered by VDD_SPI or VDD3P3_CPU; input enabled at reset |
| 37 | SPICLK_P | tri_state | Differential SPI clock positive for 8-line octal SPI mode (DQ2); GPIO47 routing via GPIO matrix available; powered by VDD_SPI or VDD3P3_CPU; input enabled at reset |
| 38 | GPIO33 | bidirectional | General-purpose digital I/O pin; SPI data line DQ4 in 8-line octal SPI mode; powered by VDD_SPI or VDD3P3_CPU; can route FSPI HD or SUBSPI HD, input enabled at reset |
| 39 | GPIO34 | bidirectional | General-purpose digital I/O pin; SPI data line DQ5 in 8-line octal SPI mode; powered by VDD_SPI or VDD3P3_CPU; can route FSPI CS0 or SUBSPI CS0, input enabled at reset |
| 40 | GPIO35 | bidirectional | General-purpose digital I/O pin; SPI data line DQ6 in 8-line octal SPI mode; powered by VDD_SPI or VDD3P3_CPU; can route FSPI D or SUBSPI D, input enabled at reset |
| 41 | GPIO36 | bidirectional | General-purpose digital I/O pin; SPI data line DQ7 in 8-line octal SPI mode; powered by VDD_SPI or VDD3P3_CPU; can route FSPI CLK or SUBSPI CLK, input enabled at reset |
| 42 | GPIO37 | bidirectional | General-purpose digital I/O pin; SPI DQS/DM line in 8-line octal SPI mode; powered by VDD_SPI or VDD3P3_CPU; can route FSPI Q or SUBSPI Q, input enabled at reset |
| 43 | GPIO38 | bidirectional | General-purpose digital I/O pin; optional external USB PHY interface pin; powered by VDD3P3_CPU; can route FSPI WP or SUBSPI WP, input enabled at reset |
| 44 | MTCK | input | JTAG test clock input; GPIO39 routing via GPIO matrix available; powered by VDD3P3_CPU; input configuration subject to EFUSE_DIS_PAD_JTAG bit |
| 45 | MTDO | tri_state | JTAG test data output in tri-state; GPIO40 routing via GPIO matrix available; powered by VDD3P3_CPU; input enabled at reset |
| 46 | VDD3P3_CPU | power_in | Digital power domain supply input, recommended voltage 3.0 to 3.3 V (do not exceed 3.3 V when writing eFuses) |
| 47 | MTDI | input | JTAG test data input; GPIO41 routing via GPIO matrix available; powered by VDD3P3_CPU; input configuration subject to EFUSE_DIS_PAD_JTAG bit |
| 48 | MTMS | input | JTAG test mode select input; GPIO42 routing via GPIO matrix available; powered by VDD3P3_CPU; input configuration subject to EFUSE_DIS_PAD_JTAG bit |
| 49 | U0TXD | output | UART0 transmit data output; GPIO43 routing via GPIO matrix available; powered by VDD3P3_CPU; internal weak pull-up enabled at reset |
| 50 | U0RXD | input | UART0 receive data input; GPIO44 routing via GPIO matrix available; powered by VDD3P3_CPU; internal weak pull-up enabled at reset |
| 51 | GPIO45 | bidirectional | General-purpose digital I/O pin; strapping pin for VDD_SPI voltage control (0 = 3.3 V, 1 = 1.8 V when EFUSE_VDD_SPI_FORCE = 0); powered by VDD3P3_CPU; internal weak pull-down enabled at reset |
| 52 | GPIO46 | bidirectional | General-purpose digital I/O pin; strapping pin for chip boot mode control and ROM messages printing; powered by VDD3P3_CPU; internal weak pull-down enabled at reset |
| 53 | XTAL_N | passive | External main crystal oscillator negative terminal for main system clock input/output, required for chip operation |
| 54 | XTAL_P | passive | External main crystal oscillator positive terminal for main system clock input/output, required for chip operation |
| 55 | VDDA | power_in | Analog power domain supply input, recommended voltage 3.0 to 3.6 V |
| 56 | VDDA | power_in | Analog power domain supply input, recommended voltage 3.0 to 3.6 V |
| 57 | GND | power_in | Ground connection; external ground reference for the chip and power return path |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Espressif Systems |
| Package | QFN-56(7x7) |
| Category | RF And Wireless |
| Pins | 57 |
CAD (KiCad official)
- Symbol:
ESP32-S3R8 - Footprint:
Package_DFN_QFN:QFN-56-1EP_7x7mm_P0.4mm_EP4x4mm - 3D model: QFN-56(7x7) (KiCad packages3D, STEP)
- 3D model files:
esp32-s3r8-etched.step/esp32-s3r8-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);esp32-s3r8.step/esp32-s3r8.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Espressif Systems datasheet (75 pp, sha256
049b83bbf484ebe9, retrieved 2026-09-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).