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ESP32-S3FH4R2
Public Made by Adomby adom
Espressif Systems WiFi Modules, QFN-56(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ESP32-S3FH4R2
Espressif Systems · WiFi Modules · QFN-56(7x7)
ESP32-S3FH4R2 from Espressif Systems, in a QFN-56(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LNA_IN | bidirectional | Low Noise Amplifier (RF LNA) input/output signal for the 2.4 GHz RF path. |
| 2 | VDD3P3 | power_in | Analog power domain supply input, which must stay within the recommended supply range of the chip. |
| 3 | VDD3P3 | power_in | Analog power domain supply input, which must stay within the recommended supply range of the chip. |
| 4 | CHIP_PU | input | Chip enable pin: high enables the chip (powered up) and low disables it (powered down); do not leave this pin floating. |
| 5 | GPIO0 | bidirectional | Strapping pin for chip boot mode control, powered by VDD3P3_RTC, with a default weak pull-up at reset and also available as RTC_GPIO0, sar_i2c_scl_0. |
| 6 | GPIO1 | bidirectional | General-purpose IO powered by VDD3P3_RTC, also RTC_GPIO1, TOUCH1 and ADC1_CH0, with a low-level glitch of about 60 us at power-up. |
| 7 | GPIO2 | bidirectional | General-purpose IO powered by VDD3P3_RTC, also RTC_GPIO2, TOUCH2 and ADC1_CH1, with a low-level glitch of about 60 us at power-up. |
| 8 | GPIO3 | bidirectional | Strapping pin for JTAG signal source control, powered by VDD3P3_RTC, also RTC_GPIO3, TOUCH3 and ADC1_CH2, with a low-level glitch of about 60 us at power-up. |
| 9 | GPIO4 | bidirectional | General-purpose IO powered by VDD3P3_RTC, also RTC_GPIO4, TOUCH4 and ADC1_CH3, with a low-level glitch of about 60 us at power-up. |
| 10 | GPIO5 | bidirectional | General-purpose IO powered by VDD3P3_RTC, also RTC_GPIO5, TOUCH5 and ADC1_CH4, with a low-level glitch of about 60 us at power-up. |
| 11 | GPIO6 | bidirectional | General-purpose IO powered by VDD3P3_RTC, also RTC_GPIO6, TOUCH6 and ADC1_CH5, with a low-level glitch of about 60 us at power-up. |
| 12 | GPIO7 | bidirectional | General-purpose IO powered by VDD3P3_RTC, also RTC_GPIO7, TOUCH7 and ADC1_CH6, with a low-level glitch of about 60 us at power-up. |
| 13 | GPIO8 | bidirectional | General-purpose IO powered by VDD3P3_RTC, also RTC_GPIO8, TOUCH8 and ADC1_CH7, with a low-level glitch of about 60 us at power-up. |
| 14 | GPIO9 | bidirectional | General-purpose IO powered by VDD3P3_RTC with input enabled at reset, also RTC_GPIO9, TOUCH9 and ADC1_CH8, with a low-level glitch of about 60 us at power-up. |
| 15 | GPIO10 | bidirectional | General-purpose IO powered by VDD3P3_RTC with input enabled at reset, also RTC_GPIO10, TOUCH10 and ADC1_CH9, with a low-level glitch of about 60 us at power-up. |
| 16 | GPIO11 | bidirectional | General-purpose IO powered by VDD3P3_RTC with input enabled at reset, also RTC_GPIO11, TOUCH11 and ADC2_CH0, with a low-level glitch of about 60 us at power-up. |
| 17 | GPIO12 | bidirectional | General-purpose IO powered by VDD3P3_RTC with input enabled at reset, also RTC_GPIO12, TOUCH12 and ADC2_CH1, with a low-level glitch of about 60 us at power-up. |
| 18 | GPIO13 | bidirectional | General-purpose IO powered by VDD3P3_RTC with input enabled at reset, also RTC_GPIO13, TOUCH13 and ADC2_CH2, with a low-level glitch of about 60 us at power-up. |
| 19 | GPIO14 | bidirectional | General-purpose IO powered by VDD3P3_RTC with input enabled at reset, also RTC_GPIO14, TOUCH14 and ADC2_CH3, with a low-level glitch of about 60 us at power-up. |
| 20 | VDD3P3_RTC | power_in | Input supply for the RTC and part of the digital power domains, which also powers the RTC IO pins. |
| 21 | XTAL_32K_P | bidirectional | 32 kHz external clock positive pin connected to the oscillator, also GPIO15, RTC_GPIO15, U0RTS and ADC2_CH4. |
| 22 | XTAL_32K_N | bidirectional | 32 kHz external clock negative pin connected to the oscillator, also GPIO16, RTC_GPIO16, U0CTS and ADC2_CH5. |
| 23 | GPIO17 | bidirectional | General-purpose IO with a default drive strength of 10 mA, powered by VDD3P3_RTC, also RTC_GPIO17, ADC2_CH6 and U1TXD. |
| 24 | GPIO18 | bidirectional | General-purpose IO with a default drive strength of 10 mA, powered by VDD3P3_RTC, also RTC_GPIO18, ADC2_CH7, U1RXD and CLK_OUT3. |
| 25 | GPIO19 | bidirectional | USB_D- signal of the USB Serial/JTAG and USB OTG interface with a default drive strength of 40 mA, also GPIO19, RTC_GPIO19, ADC2_CH8 and U1RTS. |
| 26 | GPIO20 | bidirectional | USB_D+ signal of the USB Serial/JTAG and USB OTG interface with a default drive strength of 40 mA and USB pull-up enabled at reset, also GPIO20, RTC_GPIO20, ADC2_CH9 and U1CTS. |
| 27 | GPIO21 | bidirectional | General-purpose IO powered by VDD3P3_RTC, also RTC_GPIO21. |
| 28 | SPICS1 | bidirectional | Chip select 1 for in-package PSRAM (CE#), powered by VDD_SPI with pull-up and input enabled at reset, and reserved for in-package memory. |
| 29 | VDD_SPI | power_in | Backup power line for in-package memory, which can also act as the output supply for in-package and off-package flash/PSRAM SPI IO. |
| 30 | SPIHD | bidirectional | Hold signal for in-package flash/PSRAM, powered by VDD_SPI with pull-up and input enabled at reset, and not to be used for other purposes. |
| 31 | SPIWP | bidirectional | Write protect signal for in-package flash/PSRAM, powered by VDD_SPI with pull-up and input enabled at reset, and not to be used for other purposes. |
| 32 | SPICS0 | bidirectional | Chip select 0 for in-package flash (CS#), powered by VDD_SPI with pull-up and input enabled at reset, and not to be used for other purposes. |
| 33 | SPICLK | bidirectional | Clock signal for in-package flash/PSRAM, powered by VDD_SPI with pull-up and input enabled at reset, and not to be used for other purposes. |
| 34 | SPIQ | bidirectional | Data output (SO/SIO1) for in-package flash/PSRAM, powered by VDD_SPI with pull-up and input enabled at reset, and not to be used for other purposes. |
| 35 | SPID | bidirectional | Data input (SI/SIO0) for in-package flash/PSRAM, powered by VDD_SPI with pull-up and input enabled at reset, and not to be used for other purposes. |
| 36 | SPICLK_N | bidirectional | Differential negative SPI clock, powered by VDD_SPI or VDD3P3_CPU and also available as GPIO48, with input enabled at reset. |
| 37 | SPICLK_P | bidirectional | Differential positive SPI clock, powered by VDD_SPI or VDD3P3_CPU and also available as GPIO47, with input enabled at reset. |
| 38 | GPIO33 | bidirectional | General-purpose IO powered by VDD_SPI or VDD3P3_CPU that carries the DQ4 data line for 8-line SPI and can be used as GPIO only if no flash or PSRAM uses 8-line SPI mode. |
| 39 | GPIO34 | bidirectional | General-purpose IO powered by VDD_SPI or VDD3P3_CPU that carries the DQ5 data line for 8-line SPI and can be used as GPIO only if no flash or PSRAM uses 8-line SPI mode. |
| 40 | GPIO35 | bidirectional | General-purpose IO powered by VDD_SPI or VDD3P3_CPU that carries the DQ6 data line for 8-line SPI and can be used as GPIO only if no flash or PSRAM uses 8-line SPI mode. |
| 41 | GPIO36 | bidirectional | General-purpose IO powered by VDD_SPI or VDD3P3_CPU that carries the DQ7 data line for 8-line SPI and can be used as GPIO only if no flash or PSRAM uses 8-line SPI mode. |
| 42 | GPIO37 | bidirectional | General-purpose IO powered by VDD_SPI or VDD3P3_CPU that carries the DQS/DM strobe for 8-line SPI and can be used as GPIO only if no flash or PSRAM uses 8-line SPI mode. |
| 43 | GPIO38 | bidirectional | General-purpose IO powered by VDD3P3_CPU with input enabled at reset. |
| 44 | MTCK | bidirectional | JTAG test clock pin powered by VDD3P3_CPU, also GPIO39, and its pull-up depends on the EFUSE_DIS_PAD_JTAG setting. |
| 45 | MTDO | bidirectional | JTAG test data output pin powered by VDD3P3_CPU, also GPIO40, with input enabled at reset. |
| 46 | VDD3P3_CPU | power_in | Digital power domain supply input for the digital IO pins. |
| 47 | MTDI | bidirectional | JTAG test data input pin powered by VDD3P3_CPU, also GPIO41, with input enabled at reset. |
| 48 | MTMS | bidirectional | JTAG test mode select pin powered by VDD3P3_CPU, also GPIO42, with input enabled at reset. |
| 49 | U0TXD | bidirectional | UART0 transmit data pin powered by VDD3P3_CPU with a default weak pull-up at reset, also GPIO43. |
| 50 | U0RXD | bidirectional | UART0 receive data pin powered by VDD3P3_CPU with a default weak pull-up at reset, also GPIO44. |
| 51 | GPIO45 | bidirectional | Strapping pin powered by VDD3P3_CPU with a default weak pull-down at reset, controlling the VDD_SPI voltage. |
| 52 | GPIO46 | bidirectional | Strapping pin powered by VDD3P3_CPU with a default weak pull-down at reset, controlling chip boot mode and ROM message printing. |
| 53 | XTAL_N | passive | External clock input/output connected to the chip crystal or oscillator, as the negative side of the differential clock. |
| 54 | XTAL_P | passive | External clock input/output connected to the chip crystal or oscillator, as the positive side of the differential clock. |
| 55 | VDDA | power_in | Analog power domain supply input. |
| 56 | VDDA | power_in | Analog power domain supply input. |
| 57 | GND | power_in | External ground connection for the chip. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Espressif Systems |
| Package | QFN-56(7x7) |
| Category | IoT/Communication Modules |
| Pins | 57 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Allowed input voltage (input power pins) | -0.3 | 3.6 | V | 64 | |||
| Cumulative IO output current | 1500 | mA | 64 | ||||
| Storage temperature | -40 | 150 | °C | 64 | |||
| Recommended input voltage | VDDA, VDD3P3 | 3 | 3.3 | 3.6 | V | 64 | |
| Recommended input voltage | VDD_SPI (as input) | 1.8 | 3.3 | 3.6 | V | as input | 64 |
| Cumulative input current | IVDD | 0.5 | A | 64 | |||
| DNL (Differential nonlinearity) | DNL | -4 | 4 | LSB | 66 | ||
| INL (Integral nonlinearity) | INL | -8 | 8 | LSB | 66 | ||
| Sampling rate | 100 | kSPS | 66 | ||||
| Total error | -5 | 5 | mV | ATTEN0, effective measurement range of 0 ~ 850 | 66 | ||
| Total error | -6 | 6 | mV | ATTEN1, effective measurement range of 0 ~ 1100 | 66 | ||
| Total error | -10 | 10 | mV | ATTEN2, effective measurement range of 0 ~ 1600 | 66 | ||
| Total error | -50 | 50 | mV | ATTEN3, effective measurement range of 0 ~ 2900 | 66 | ||
| Power supply voltage (1.8 V) flash | VCC | 1.65 | 1.8 | 2 | V | 68 | |
| Power supply voltage (3.3 V) flash | VCC | 2.7 | 3.3 | 3.6 | V | 68 | |
| Power supply voltage (1.8 V) PSRAM | VCC | 1.62 | 1.8 | 1.98 | V | 69 | |
| Power supply voltage (3.3 V) PSRAM | VCC | 2.7 | 3.3 | 3.6 | V | 69 | |
| Pin capacitance | CIN | 2 | pF | 65 | |||
| High-level input current | IIH | 50 | nA | 65 | |||
| Low-level input current | IIL | 50 | nA | 65 | |||
| Internal weak pull-up resistor | RPU | 45 | kΩ | 65 | |||
| Internal weak pull-down resistor | RPD | 45 | kΩ | 65 | |||
| VDD_SPI powered by VDD3P3_RTC via RSPI for 3.3 V flash/PSRAM | RSPI | 14 | Ω | VDD_SPI powered by VDD3P3_RTC via RSPI for 3.3 V flash/PSRAM | 65 | ||
| Output current when VDD_SPI is powered by Flash Voltage Regulator for 1.8 V flash/PSRAM | ISPI | 40 | mA | Output current when VDD_SPI is powered by Flash Voltage Regulator for 1.8 V flash/PSRAM | 65 | ||
| High-level source current | IOH | 40 | mA | VDD = 3.3 V, VOH >= 2.64 V, PAD_DRIVER = 3 | 65 | ||
| Low-level sink current | IOL | 28 | mA | VDD = 3.3 V, VOL = 0.495 V, PAD_DRIVER = 3 | 65 | ||
| Light-sleep current | 240 | µA | VDD_SPI and Wi-Fi are powered down, and all GPIOs are high-impedance | 68 | |||
| Deep-sleep power off current | 1 | µA | CHIP_PU is set to low level. The chip is shut down. | 68 |
CAD (KiCad official)
- Symbol:
ESP32-S3FH4R2 - Footprint:
Package_DFN_QFN:QFN-56-1EP_7x7mm_P0.4mm_EP5.6x5.6mm - 3D model: QFN-56(7x7) (KiCad packages3D, STEP)
- 3D model files:
esp32-s3fh4r2-etched.step/esp32-s3fh4r2-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);esp32-s3fh4r2.step/esp32-s3fh4r2.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Espressif Systems datasheet (87 pp, sha256
2d5a7cb7fd559d8d, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ESP32-S3FH4R2
**Espressif Systems** · WiFi Modules · QFN-56(7x7)
ESP32-S3FH4R2 from Espressif Systems, in a QFN-56(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LNA_IN | bidirectional | Low Noise Amplifier (RF LNA) input/output signal for the 2.4 GHz RF path. |
| 2 | VDD3P3 | power_in | Analog power domain supply input, which must stay within the recommended supply range of the chip. |
| 3 | VDD3P3 | power_in | Analog power domain supply input, which must stay within the recommended supply range of the chip. |
| 4 | CHIP_PU | input | Chip enable pin: high enables the chip (powered up) and low disables it (powered down); do not leave this pin floating. |
| 5 | GPIO0 | bidirectional | Strapping pin for chip boot mode control, powered by VDD3P3_RTC, with a default weak pull-up at reset and also available as RTC_GPIO0, sar_i2c_scl_0. |
| 6 | GPIO1 | bidirectional | General-purpose IO powered by VDD3P3_RTC, also RTC_GPIO1, TOUCH1 and ADC1_CH0, with a low-level glitch of about 60 us at power-up. |
| 7 | GPIO2 | bidirectional | General-purpose IO powered by VDD3P3_RTC, also RTC_GPIO2, TOUCH2 and ADC1_CH1, with a low-level glitch of about 60 us at power-up. |
| 8 | GPIO3 | bidirectional | Strapping pin for JTAG signal source control, powered by VDD3P3_RTC, also RTC_GPIO3, TOUCH3 and ADC1_CH2, with a low-level glitch of about 60 us at power-up. |
| 9 | GPIO4 | bidirectional | General-purpose IO powered by VDD3P3_RTC, also RTC_GPIO4, TOUCH4 and ADC1_CH3, with a low-level glitch of about 60 us at power-up. |
| 10 | GPIO5 | bidirectional | General-purpose IO powered by VDD3P3_RTC, also RTC_GPIO5, TOUCH5 and ADC1_CH4, with a low-level glitch of about 60 us at power-up. |
| 11 | GPIO6 | bidirectional | General-purpose IO powered by VDD3P3_RTC, also RTC_GPIO6, TOUCH6 and ADC1_CH5, with a low-level glitch of about 60 us at power-up. |
| 12 | GPIO7 | bidirectional | General-purpose IO powered by VDD3P3_RTC, also RTC_GPIO7, TOUCH7 and ADC1_CH6, with a low-level glitch of about 60 us at power-up. |
| 13 | GPIO8 | bidirectional | General-purpose IO powered by VDD3P3_RTC, also RTC_GPIO8, TOUCH8 and ADC1_CH7, with a low-level glitch of about 60 us at power-up. |
| 14 | GPIO9 | bidirectional | General-purpose IO powered by VDD3P3_RTC with input enabled at reset, also RTC_GPIO9, TOUCH9 and ADC1_CH8, with a low-level glitch of about 60 us at power-up. |
| 15 | GPIO10 | bidirectional | General-purpose IO powered by VDD3P3_RTC with input enabled at reset, also RTC_GPIO10, TOUCH10 and ADC1_CH9, with a low-level glitch of about 60 us at power-up. |
| 16 | GPIO11 | bidirectional | General-purpose IO powered by VDD3P3_RTC with input enabled at reset, also RTC_GPIO11, TOUCH11 and ADC2_CH0, with a low-level glitch of about 60 us at power-up. |
| 17 | GPIO12 | bidirectional | General-purpose IO powered by VDD3P3_RTC with input enabled at reset, also RTC_GPIO12, TOUCH12 and ADC2_CH1, with a low-level glitch of about 60 us at power-up. |
| 18 | GPIO13 | bidirectional | General-purpose IO powered by VDD3P3_RTC with input enabled at reset, also RTC_GPIO13, TOUCH13 and ADC2_CH2, with a low-level glitch of about 60 us at power-up. |
| 19 | GPIO14 | bidirectional | General-purpose IO powered by VDD3P3_RTC with input enabled at reset, also RTC_GPIO14, TOUCH14 and ADC2_CH3, with a low-level glitch of about 60 us at power-up. |
| 20 | VDD3P3_RTC | power_in | Input supply for the RTC and part of the digital power domains, which also powers the RTC IO pins. |
| 21 | XTAL_32K_P | bidirectional | 32 kHz external clock positive pin connected to the oscillator, also GPIO15, RTC_GPIO15, U0RTS and ADC2_CH4. |
| 22 | XTAL_32K_N | bidirectional | 32 kHz external clock negative pin connected to the oscillator, also GPIO16, RTC_GPIO16, U0CTS and ADC2_CH5. |
| 23 | GPIO17 | bidirectional | General-purpose IO with a default drive strength of 10 mA, powered by VDD3P3_RTC, also RTC_GPIO17, ADC2_CH6 and U1TXD. |
| 24 | GPIO18 | bidirectional | General-purpose IO with a default drive strength of 10 mA, powered by VDD3P3_RTC, also RTC_GPIO18, ADC2_CH7, U1RXD and CLK_OUT3. |
| 25 | GPIO19 | bidirectional | USB_D- signal of the USB Serial/JTAG and USB OTG interface with a default drive strength of 40 mA, also GPIO19, RTC_GPIO19, ADC2_CH8 and U1RTS. |
| 26 | GPIO20 | bidirectional | USB_D+ signal of the USB Serial/JTAG and USB OTG interface with a default drive strength of 40 mA and USB pull-up enabled at reset, also GPIO20, RTC_GPIO20, ADC2_CH9 and U1CTS. |
| 27 | GPIO21 | bidirectional | General-purpose IO powered by VDD3P3_RTC, also RTC_GPIO21. |
| 28 | SPICS1 | bidirectional | Chip select 1 for in-package PSRAM (CE#), powered by VDD_SPI with pull-up and input enabled at reset, and reserved for in-package memory. |
| 29 | VDD_SPI | power_in | Backup power line for in-package memory, which can also act as the output supply for in-package and off-package flash/PSRAM SPI IO. |
| 30 | SPIHD | bidirectional | Hold signal for in-package flash/PSRAM, powered by VDD_SPI with pull-up and input enabled at reset, and not to be used for other purposes. |
| 31 | SPIWP | bidirectional | Write protect signal for in-package flash/PSRAM, powered by VDD_SPI with pull-up and input enabled at reset, and not to be used for other purposes. |
| 32 | SPICS0 | bidirectional | Chip select 0 for in-package flash (CS#), powered by VDD_SPI with pull-up and input enabled at reset, and not to be used for other purposes. |
| 33 | SPICLK | bidirectional | Clock signal for in-package flash/PSRAM, powered by VDD_SPI with pull-up and input enabled at reset, and not to be used for other purposes. |
| 34 | SPIQ | bidirectional | Data output (SO/SIO1) for in-package flash/PSRAM, powered by VDD_SPI with pull-up and input enabled at reset, and not to be used for other purposes. |
| 35 | SPID | bidirectional | Data input (SI/SIO0) for in-package flash/PSRAM, powered by VDD_SPI with pull-up and input enabled at reset, and not to be used for other purposes. |
| 36 | SPICLK_N | bidirectional | Differential negative SPI clock, powered by VDD_SPI or VDD3P3_CPU and also available as GPIO48, with input enabled at reset. |
| 37 | SPICLK_P | bidirectional | Differential positive SPI clock, powered by VDD_SPI or VDD3P3_CPU and also available as GPIO47, with input enabled at reset. |
| 38 | GPIO33 | bidirectional | General-purpose IO powered by VDD_SPI or VDD3P3_CPU that carries the DQ4 data line for 8-line SPI and can be used as GPIO only if no flash or PSRAM uses 8-line SPI mode. |
| 39 | GPIO34 | bidirectional | General-purpose IO powered by VDD_SPI or VDD3P3_CPU that carries the DQ5 data line for 8-line SPI and can be used as GPIO only if no flash or PSRAM uses 8-line SPI mode. |
| 40 | GPIO35 | bidirectional | General-purpose IO powered by VDD_SPI or VDD3P3_CPU that carries the DQ6 data line for 8-line SPI and can be used as GPIO only if no flash or PSRAM uses 8-line SPI mode. |
| 41 | GPIO36 | bidirectional | General-purpose IO powered by VDD_SPI or VDD3P3_CPU that carries the DQ7 data line for 8-line SPI and can be used as GPIO only if no flash or PSRAM uses 8-line SPI mode. |
| 42 | GPIO37 | bidirectional | General-purpose IO powered by VDD_SPI or VDD3P3_CPU that carries the DQS/DM strobe for 8-line SPI and can be used as GPIO only if no flash or PSRAM uses 8-line SPI mode. |
| 43 | GPIO38 | bidirectional | General-purpose IO powered by VDD3P3_CPU with input enabled at reset. |
| 44 | MTCK | bidirectional | JTAG test clock pin powered by VDD3P3_CPU, also GPIO39, and its pull-up depends on the EFUSE_DIS_PAD_JTAG setting. |
| 45 | MTDO | bidirectional | JTAG test data output pin powered by VDD3P3_CPU, also GPIO40, with input enabled at reset. |
| 46 | VDD3P3_CPU | power_in | Digital power domain supply input for the digital IO pins. |
| 47 | MTDI | bidirectional | JTAG test data input pin powered by VDD3P3_CPU, also GPIO41, with input enabled at reset. |
| 48 | MTMS | bidirectional | JTAG test mode select pin powered by VDD3P3_CPU, also GPIO42, with input enabled at reset. |
| 49 | U0TXD | bidirectional | UART0 transmit data pin powered by VDD3P3_CPU with a default weak pull-up at reset, also GPIO43. |
| 50 | U0RXD | bidirectional | UART0 receive data pin powered by VDD3P3_CPU with a default weak pull-up at reset, also GPIO44. |
| 51 | GPIO45 | bidirectional | Strapping pin powered by VDD3P3_CPU with a default weak pull-down at reset, controlling the VDD_SPI voltage. |
| 52 | GPIO46 | bidirectional | Strapping pin powered by VDD3P3_CPU with a default weak pull-down at reset, controlling chip boot mode and ROM message printing. |
| 53 | XTAL_N | passive | External clock input/output connected to the chip crystal or oscillator, as the negative side of the differential clock. |
| 54 | XTAL_P | passive | External clock input/output connected to the chip crystal or oscillator, as the positive side of the differential clock. |
| 55 | VDDA | power_in | Analog power domain supply input. |
| 56 | VDDA | power_in | Analog power domain supply input. |
| 57 | GND | power_in | External ground connection for the chip. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Espressif Systems |
| Package | QFN-56(7x7) |
| Category | IoT/Communication Modules |
| Pins | 57 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Allowed input voltage (input power pins) | | -0.3 | | 3.6 | V | | 64 |
| Cumulative IO output current | | | | 1500 | mA | | 64 |
| Storage temperature | | -40 | | 150 | °C | | 64 |
| Recommended input voltage | VDDA, VDD3P3 | 3 | 3.3 | 3.6 | V | | 64 |
| Recommended input voltage | VDD_SPI (as input) | 1.8 | 3.3 | 3.6 | V | as input | 64 |
| Cumulative input current | IVDD | 0.5 | | | A | | 64 |
| DNL (Differential nonlinearity) | DNL | -4 | | 4 | LSB | | 66 |
| INL (Integral nonlinearity) | INL | -8 | | 8 | LSB | | 66 |
| Sampling rate | | | | 100 | kSPS | | 66 |
| Total error | | -5 | | 5 | mV | ATTEN0, effective measurement range of 0 ~ 850 | 66 |
| Total error | | -6 | | 6 | mV | ATTEN1, effective measurement range of 0 ~ 1100 | 66 |
| Total error | | -10 | | 10 | mV | ATTEN2, effective measurement range of 0 ~ 1600 | 66 |
| Total error | | -50 | | 50 | mV | ATTEN3, effective measurement range of 0 ~ 2900 | 66 |
| Power supply voltage (1.8 V) flash | VCC | 1.65 | 1.8 | 2 | V | | 68 |
| Power supply voltage (3.3 V) flash | VCC | 2.7 | 3.3 | 3.6 | V | | 68 |
| Power supply voltage (1.8 V) PSRAM | VCC | 1.62 | 1.8 | 1.98 | V | | 69 |
| Power supply voltage (3.3 V) PSRAM | VCC | 2.7 | 3.3 | 3.6 | V | | 69 |
| Pin capacitance | CIN | | 2 | | pF | | 65 |
| High-level input current | IIH | | | 50 | nA | | 65 |
| Low-level input current | IIL | | | 50 | nA | | 65 |
| Internal weak pull-up resistor | RPU | | 45 | | kΩ | | 65 |
| Internal weak pull-down resistor | RPD | | 45 | | kΩ | | 65 |
| VDD_SPI powered by VDD3P3_RTC via RSPI for 3.3 V flash/PSRAM | RSPI | | 14 | | Ω | VDD_SPI powered by VDD3P3_RTC via RSPI for 3.3 V flash/PSRAM | 65 |
| Output current when VDD_SPI is powered by Flash Voltage Regulator for 1.8 V flash/PSRAM | ISPI | | 40 | | mA | Output current when VDD_SPI is powered by Flash Voltage Regulator for 1.8 V flash/PSRAM | 65 |
| High-level source current | IOH | | 40 | | mA | VDD = 3.3 V, VOH >= 2.64 V, PAD_DRIVER = 3 | 65 |
| Low-level sink current | IOL | | 28 | | mA | VDD = 3.3 V, VOL = 0.495 V, PAD_DRIVER = 3 | 65 |
| Light-sleep current | | | 240 | | µA | VDD_SPI and Wi-Fi are powered down, and all GPIOs are high-impedance | 68 |
| Deep-sleep power off current | | | 1 | | µA | CHIP_PU is set to low level. The chip is shut down. | 68 |
## CAD (KiCad official)
- Symbol: `ESP32-S3FH4R2`
- Footprint: `Package_DFN_QFN:QFN-56-1EP_7x7mm_P0.4mm_EP5.6x5.6mm`
- 3D model: QFN-56(7x7) (KiCad packages3D, STEP)
- 3D model files: `esp32-s3fh4r2-etched.step` / `esp32-s3fh4r2-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `esp32-s3fh4r2.step` / `esp32-s3fh4r2.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Espressif Systems datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf) (87 pp, sha256 `2d5a7cb7fd559d8d`, retrieved 2026-10-27, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/esp32-s3fh4r2-datasheet.pdf)