component
ESP32-S3
Public Made by Adomby adom
Espressif Systems RF Transceiver ICs, QFN-56-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ESP32-S3
Espressif Systems · RF Transceiver ICs · QFN-56-EP(7x7)
ESP32-S3 from Espressif Systems, in a QFN-56-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LNA_IN | passive | RF low-noise amplifier input/output signal. |
| 2 | VDD3P3 | power_in | Analog power domain supply input, recommended 3.0 V to 3.6 V with 3.3 V typical. |
| 3 | VDD3P3 | power_in | Analog power domain supply input, recommended 3.0 V to 3.6 V with 3.3 V typical. |
| 4 | CHIP_PU | input | High level enables the chip and low level powers it down; the pin must not be left floating. |
| 5 | GPIO0 | bidirectional | General-purpose I/O and RTC_GPIO0; strapping pin with GPIO46 that selects the boot mode, with a default weak pull-up. |
| 6 | GPIO1 | bidirectional | General-purpose I/O with RTC_GPIO1, TOUCH1 and ADC1_CH0 functions; may output a low-level glitch of about 60 µs at power-up. |
| 7 | GPIO2 | bidirectional | General-purpose I/O with RTC_GPIO2, TOUCH2 and ADC1_CH1 functions; may output a low-level glitch of about 60 µs at power-up. |
| 8 | GPIO3 | bidirectional | General-purpose I/O with RTC_GPIO3, TOUCH3 and ADC1_CH2 functions; strapping pin for JTAG signal source selection with no internal pull resistor, so it must be driven by an external circuit that is not high-impedance. |
| 9 | GPIO4 | bidirectional | General-purpose I/O with RTC_GPIO4, TOUCH4 and ADC1_CH3 functions; may output a low-level glitch of about 60 µs at power-up. |
| 10 | GPIO5 | bidirectional | General-purpose I/O with RTC_GPIO5, TOUCH5 and ADC1_CH4 functions; may output a low-level glitch of about 60 µs at power-up. |
| 11 | GPIO6 | bidirectional | General-purpose I/O with RTC_GPIO6, TOUCH6 and ADC1_CH5 functions; may output a low-level glitch of about 60 µs at power-up. |
| 12 | GPIO7 | bidirectional | General-purpose I/O with RTC_GPIO7, TOUCH7 and ADC1_CH6 functions; may output a low-level glitch of about 60 µs at power-up. |
| 13 | GPIO8 | bidirectional | General-purpose I/O with RTC_GPIO8, TOUCH8 and ADC1_CH7 functions; may output a low-level glitch of about 60 µs at power-up. |
| 14 | GPIO9 | bidirectional | General-purpose I/O with RTC_GPIO9, TOUCH9 and ADC1_CH8 functions; may output a low-level glitch of about 60 µs at power-up. |
| 15 | GPIO10 | bidirectional | General-purpose I/O with RTC_GPIO10, TOUCH10 and ADC1_CH9 functions; may output a low-level glitch of about 60 µs at power-up. |
| 16 | GPIO11 | bidirectional | General-purpose I/O with RTC_GPIO11, TOUCH11 and ADC2_CH0 functions; may output a low-level glitch of about 60 µs at power-up. |
| 17 | GPIO12 | bidirectional | General-purpose I/O with RTC_GPIO12, TOUCH12 and ADC2_CH1 functions; may output a low-level glitch of about 60 µs at power-up. |
| 18 | GPIO13 | bidirectional | General-purpose I/O with RTC_GPIO13, TOUCH13 and ADC2_CH2 functions; may output a low-level glitch of about 60 µs at power-up. |
| 19 | GPIO14 | bidirectional | General-purpose I/O with RTC_GPIO14, TOUCH14 and ADC2_CH3 functions; may output a low-level glitch of about 60 µs at power-up. |
| 20 | VDD3P3_RTC | power_in | Supply for the RTC and part of the digital power domain, recommended 3.0 V to 3.6 V with 3.3 V typical. |
| 21 | XTAL_32K_P | bidirectional | Positive terminal of the external 32 kHz clock, also GPIO15/RTC_GPIO15 and ADC2_CH4; may output a low-level glitch of about 60 µs at power-up. |
| 22 | XTAL_32K_N | bidirectional | Negative terminal of the external 32 kHz clock, also GPIO16/RTC_GPIO16 and ADC2_CH5; may output a low-level glitch of about 60 µs at power-up. |
| 23 | GPIO17 | bidirectional | General-purpose I/O with RTC_GPIO17, ADC2_CH6 and UART1 TXD function, with a default drive current of 10 mA. |
| 24 | GPIO18 | bidirectional | General-purpose I/O with RTC_GPIO18, ADC2_CH7 and UART1 RXD function, with a default drive current of 10 mA. |
| 25 | GPIO19 | bidirectional | General-purpose I/O that doubles as USB_D- (with RTC_GPIO19 and ADC2_CH8), with a default drive current of 40 mA. |
| 26 | GPIO20 | bidirectional | General-purpose I/O that doubles as USB_D+ (with RTC_GPIO20 and ADC2_CH9), with a default drive current of 40 mA and USB pull-up enabled by default. |
| 27 | GPIO21 | bidirectional | General-purpose I/O with RTC_GPIO21 function, powered from VDD3P3_RTC. |
| 28 | SPICS1 | bidirectional | SPI chip-select 1 (GPIO26) used to connect the in-package PSRAM chip enable; it is powered from VDD_SPI, and the datasheet advises not to use the flash/PSRAM-connected pins for other purposes. |
| 29 | VDD_SPI | power_out | Supply for the in-package memory and flash/PSRAM SPI I/O; it can also be configured as an input from VDD3P3_RTC, with the voltage set by eFuse and strapping as described in the datasheet. |
| 30 | SPIHD | bidirectional | SPI hold signal (GPIO27) connected to flash HOLD# or PSRAM SIO3, powered from VDD_SPI. |
| 31 | SPIWP | bidirectional | SPI write-protect signal (GPIO28) connected to flash WP# or PSRAM SIO2, powered from VDD_SPI. |
| 32 | SPICS0 | bidirectional | SPI chip-select 0 (GPIO29) connected to the in-package flash CS#, powered from VDD_SPI. |
| 33 | SPICLK | bidirectional | SPI clock (GPIO30) connected to flash/PSRAM CLK, powered from VDD_SPI. |
| 34 | SPIQ | bidirectional | SPI data output (GPIO31) connected to flash DO or PSRAM SO/SIO1, powered from VDD_SPI. |
| 35 | SPID | bidirectional | SPI data input (GPIO32) connected to flash DI or PSRAM SI/SIO0, powered from VDD_SPI. |
| 36 | SPICLK_N | bidirectional | Negative differential SPI clock (also GPIO48) for octal SPI, powered from VDD_SPI or VDD3P3_CPU as selected by eFuse. |
| 37 | SPICLK_P | bidirectional | Positive differential SPI clock (also GPIO47) for octal SPI, powered from VDD_SPI or VDD3P3_CPU as selected by eFuse. |
| 38 | GPIO33 | bidirectional | General-purpose I/O (also FSPIHD, SUBSPIHD and SPIIO4), powered from VDD_SPI or VDD3P3_CPU as selected by eFuse. |
| 39 | GPIO34 | bidirectional | General-purpose I/O (also FSPICS0, SUBSPICS0 and SPIIO5), powered from VDD_SPI or VDD3P3_CPU as selected by eFuse. |
| 40 | GPIO35 | bidirectional | General-purpose I/O (also FSPID, SUBSPID and SPIIO6), powered from VDD_SPI or VDD3P3_CPU as selected by eFuse. |
| 41 | GPIO36 | bidirectional | General-purpose I/O (also FSPICLK, SUBSPICLK and SPIIO7), powered from VDD_SPI or VDD3P3_CPU as selected by eFuse. |
| 42 | GPIO37 | bidirectional | General-purpose I/O (also FSPIQ, SUBSPIQ and SPIDQS), powered from VDD_SPI or VDD3P3_CPU as selected by eFuse. |
| 43 | GPIO38 | bidirectional | General-purpose I/O (also FSPIWP and SUBSPIWP), powered from VDD3P3_CPU. |
| 44 | MTCK | bidirectional | JTAG test clock (also GPIO39, CLK_OUT3 and SUBSPICS1), powered from VDD3P3_CPU with input enabled. |
| 45 | MTDO | bidirectional | JTAG test data output (also GPIO40 and CLK_OUT2), powered from VDD3P3_CPU. |
| 46 | VDD3P3_CPU | power_in | Digital power domain supply, recommended 3.0 V to 3.6 V with 3.3 V typical; the datasheet says it must not exceed 3.3 V when writing eFuse. |
| 47 | MTDI | bidirectional | JTAG test data input (also GPIO41 and CLK_OUT1), powered from VDD3P3_CPU. |
| 48 | MTMS | bidirectional | JTAG test mode select (also GPIO42), powered from VDD3P3_CPU. |
| 49 | U0TXD | bidirectional | UART0 transmit (also GPIO43 and CLK_OUT1), powered from VDD3P3_CPU with a default weak pull-up. |
| 50 | U0RXD | bidirectional | UART0 receive (also GPIO44 and CLK_OUT2), powered from VDD3P3_CPU with a default weak pull-up. |
| 51 | GPIO45 | bidirectional | General-purpose I/O and strapping pin that sets the VDD_SPI voltage, with a default weak pull-down. |
| 52 | GPIO46 | bidirectional | General-purpose I/O and strapping pin that works with GPIO0 for boot mode and controls ROM log printing, with a default weak pull-down. |
| 53 | XTAL_N | passive | Negative side of the external clock input/output for an active or passive crystal. |
| 54 | XTAL_P | passive | Positive side of the external clock input/output for an active or passive crystal. |
| 55 | VDDA | power_in | Analog power domain supply, recommended 3.0 V to 3.6 V with 3.3 V typical. |
| 56 | VDDA | power_in | Analog power domain supply, recommended 3.0 V to 3.6 V with 3.3 V typical. |
| 57 | GND | power_in | Ground, connected to the exposed pad of the QFN56 package. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Espressif Systems |
| Package | QFN-56-EP(7x7) |
| Category | RF And Wireless |
| Pins | 57 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Allowable input voltage (power supply pins) | -0.3 | 3.6 | V | 60 | |||
| IO output total current | Ioutput | 1500 | mA | 60 | |||
| Storage temperature | TSTORE | -40 | 150 | °C | 60 | ||
| Recommended input voltage (VDDA, VDD3P3) | VDDA, VDD3P3 | 3 | 3.3 | 3.6 | V | 60 | |
| Recommended input voltage (VDD3P3_RTC) | VDD3P3_RTC | 3 | 3.3 | 3.6 | V | 60 | |
| Recommended input voltage (VDD_SPI input) | VDD_SPI | 1.8 | 3.3 | 3.6 | V | 60 | |
| Recommended input voltage (VDD3P3_CPU) | VDD3P3_CPU | 3 | 3.3 | 3.6 | V | 60 | |
| Input total current | IVDD | 0.5 | A | 使用单电源供电时 | 60 | ||
| Low-level input voltage | VIL | -0.3 | V | 61 | |||
| High-level input current | IIH | 50 | nA | 61 | |||
| Low-level input current | IIL | 50 | nA | 61 | |||
| Chip reset voltage (low) | VIL_nRST | -0.3 | V | CHIP_PU 应满足电压范围 | 61 | ||
| DNL (differential nonlinearity) | DNL | -4 | 4 | LSB | 62 | ||
| INL (integral nonlinearity) | INL | -8 | 8 | LSB | 62 | ||
| Sampling speed | 100 | kSPS | 62 | ||||
| ADC total error (ATTEN0) | -5 | 5 | mV | ATTEN0，有效测量范围为 0 ~ 850 | 62 | ||
| ADC total error (ATTEN1) | -6 | 6 | mV | ATTEN1，有效测量范围为 0 ~ 1100 | 62 | ||
| ADC total error (ATTEN2) | -10 | 10 | mV | ATTEN2，有效测量范围为 0 ~ 1600 | 62 | ||
| ADC total error (ATTEN3) | -50 | 50 | mV | ATTEN3，有效测量范围为 0 ~ 2900 | 62 | ||
| ESD HBM (human body model) | -2000 | 2000 | V | HBM, JS-001 | 64 | ||
| ESD CDM (charged device model) | -1000 | 1000 | V | CDM, JS-002 | 64 | ||
| Latch-up current | -200 | 200 | mA | JESD78 过电流 | 64 | ||
| Wi-Fi operating channel center frequency | 2412 | 2484 | MHz | 65 |
CAD (KiCad official)
- Symbol:
ESP32-S3 - Footprint:
Package_DFN_QFN:QFN-56-1EP_7x7mm_P0.4mm_EP4x4mm - 3D model: QFN-56-EP(7x7) (KiCad packages3D, STEP)
- 3D model files:
esp32-s3-etched.step/esp32-s3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);esp32-s3.step/esp32-s3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Espressif Systems datasheet (79 pp, sha256
97b4b3199f87c43f, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ESP32-S3
**Espressif Systems** · RF Transceiver ICs · QFN-56-EP(7x7)
ESP32-S3 from Espressif Systems, in a QFN-56-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LNA_IN | passive | RF low-noise amplifier input/output signal. |
| 2 | VDD3P3 | power_in | Analog power domain supply input, recommended 3.0 V to 3.6 V with 3.3 V typical. |
| 3 | VDD3P3 | power_in | Analog power domain supply input, recommended 3.0 V to 3.6 V with 3.3 V typical. |
| 4 | CHIP_PU | input | High level enables the chip and low level powers it down; the pin must not be left floating. |
| 5 | GPIO0 | bidirectional | General-purpose I/O and RTC_GPIO0; strapping pin with GPIO46 that selects the boot mode, with a default weak pull-up. |
| 6 | GPIO1 | bidirectional | General-purpose I/O with RTC_GPIO1, TOUCH1 and ADC1_CH0 functions; may output a low-level glitch of about 60 µs at power-up. |
| 7 | GPIO2 | bidirectional | General-purpose I/O with RTC_GPIO2, TOUCH2 and ADC1_CH1 functions; may output a low-level glitch of about 60 µs at power-up. |
| 8 | GPIO3 | bidirectional | General-purpose I/O with RTC_GPIO3, TOUCH3 and ADC1_CH2 functions; strapping pin for JTAG signal source selection with no internal pull resistor, so it must be driven by an external circuit that is not high-impedance. |
| 9 | GPIO4 | bidirectional | General-purpose I/O with RTC_GPIO4, TOUCH4 and ADC1_CH3 functions; may output a low-level glitch of about 60 µs at power-up. |
| 10 | GPIO5 | bidirectional | General-purpose I/O with RTC_GPIO5, TOUCH5 and ADC1_CH4 functions; may output a low-level glitch of about 60 µs at power-up. |
| 11 | GPIO6 | bidirectional | General-purpose I/O with RTC_GPIO6, TOUCH6 and ADC1_CH5 functions; may output a low-level glitch of about 60 µs at power-up. |
| 12 | GPIO7 | bidirectional | General-purpose I/O with RTC_GPIO7, TOUCH7 and ADC1_CH6 functions; may output a low-level glitch of about 60 µs at power-up. |
| 13 | GPIO8 | bidirectional | General-purpose I/O with RTC_GPIO8, TOUCH8 and ADC1_CH7 functions; may output a low-level glitch of about 60 µs at power-up. |
| 14 | GPIO9 | bidirectional | General-purpose I/O with RTC_GPIO9, TOUCH9 and ADC1_CH8 functions; may output a low-level glitch of about 60 µs at power-up. |
| 15 | GPIO10 | bidirectional | General-purpose I/O with RTC_GPIO10, TOUCH10 and ADC1_CH9 functions; may output a low-level glitch of about 60 µs at power-up. |
| 16 | GPIO11 | bidirectional | General-purpose I/O with RTC_GPIO11, TOUCH11 and ADC2_CH0 functions; may output a low-level glitch of about 60 µs at power-up. |
| 17 | GPIO12 | bidirectional | General-purpose I/O with RTC_GPIO12, TOUCH12 and ADC2_CH1 functions; may output a low-level glitch of about 60 µs at power-up. |
| 18 | GPIO13 | bidirectional | General-purpose I/O with RTC_GPIO13, TOUCH13 and ADC2_CH2 functions; may output a low-level glitch of about 60 µs at power-up. |
| 19 | GPIO14 | bidirectional | General-purpose I/O with RTC_GPIO14, TOUCH14 and ADC2_CH3 functions; may output a low-level glitch of about 60 µs at power-up. |
| 20 | VDD3P3_RTC | power_in | Supply for the RTC and part of the digital power domain, recommended 3.0 V to 3.6 V with 3.3 V typical. |
| 21 | XTAL_32K_P | bidirectional | Positive terminal of the external 32 kHz clock, also GPIO15/RTC_GPIO15 and ADC2_CH4; may output a low-level glitch of about 60 µs at power-up. |
| 22 | XTAL_32K_N | bidirectional | Negative terminal of the external 32 kHz clock, also GPIO16/RTC_GPIO16 and ADC2_CH5; may output a low-level glitch of about 60 µs at power-up. |
| 23 | GPIO17 | bidirectional | General-purpose I/O with RTC_GPIO17, ADC2_CH6 and UART1 TXD function, with a default drive current of 10 mA. |
| 24 | GPIO18 | bidirectional | General-purpose I/O with RTC_GPIO18, ADC2_CH7 and UART1 RXD function, with a default drive current of 10 mA. |
| 25 | GPIO19 | bidirectional | General-purpose I/O that doubles as USB_D- (with RTC_GPIO19 and ADC2_CH8), with a default drive current of 40 mA. |
| 26 | GPIO20 | bidirectional | General-purpose I/O that doubles as USB_D+ (with RTC_GPIO20 and ADC2_CH9), with a default drive current of 40 mA and USB pull-up enabled by default. |
| 27 | GPIO21 | bidirectional | General-purpose I/O with RTC_GPIO21 function, powered from VDD3P3_RTC. |
| 28 | SPICS1 | bidirectional | SPI chip-select 1 (GPIO26) used to connect the in-package PSRAM chip enable; it is powered from VDD_SPI, and the datasheet advises not to use the flash/PSRAM-connected pins for other purposes. |
| 29 | VDD_SPI | power_out | Supply for the in-package memory and flash/PSRAM SPI I/O; it can also be configured as an input from VDD3P3_RTC, with the voltage set by eFuse and strapping as described in the datasheet. |
| 30 | SPIHD | bidirectional | SPI hold signal (GPIO27) connected to flash HOLD# or PSRAM SIO3, powered from VDD_SPI. |
| 31 | SPIWP | bidirectional | SPI write-protect signal (GPIO28) connected to flash WP# or PSRAM SIO2, powered from VDD_SPI. |
| 32 | SPICS0 | bidirectional | SPI chip-select 0 (GPIO29) connected to the in-package flash CS#, powered from VDD_SPI. |
| 33 | SPICLK | bidirectional | SPI clock (GPIO30) connected to flash/PSRAM CLK, powered from VDD_SPI. |
| 34 | SPIQ | bidirectional | SPI data output (GPIO31) connected to flash DO or PSRAM SO/SIO1, powered from VDD_SPI. |
| 35 | SPID | bidirectional | SPI data input (GPIO32) connected to flash DI or PSRAM SI/SIO0, powered from VDD_SPI. |
| 36 | SPICLK_N | bidirectional | Negative differential SPI clock (also GPIO48) for octal SPI, powered from VDD_SPI or VDD3P3_CPU as selected by eFuse. |
| 37 | SPICLK_P | bidirectional | Positive differential SPI clock (also GPIO47) for octal SPI, powered from VDD_SPI or VDD3P3_CPU as selected by eFuse. |
| 38 | GPIO33 | bidirectional | General-purpose I/O (also FSPIHD, SUBSPIHD and SPIIO4), powered from VDD_SPI or VDD3P3_CPU as selected by eFuse. |
| 39 | GPIO34 | bidirectional | General-purpose I/O (also FSPICS0, SUBSPICS0 and SPIIO5), powered from VDD_SPI or VDD3P3_CPU as selected by eFuse. |
| 40 | GPIO35 | bidirectional | General-purpose I/O (also FSPID, SUBSPID and SPIIO6), powered from VDD_SPI or VDD3P3_CPU as selected by eFuse. |
| 41 | GPIO36 | bidirectional | General-purpose I/O (also FSPICLK, SUBSPICLK and SPIIO7), powered from VDD_SPI or VDD3P3_CPU as selected by eFuse. |
| 42 | GPIO37 | bidirectional | General-purpose I/O (also FSPIQ, SUBSPIQ and SPIDQS), powered from VDD_SPI or VDD3P3_CPU as selected by eFuse. |
| 43 | GPIO38 | bidirectional | General-purpose I/O (also FSPIWP and SUBSPIWP), powered from VDD3P3_CPU. |
| 44 | MTCK | bidirectional | JTAG test clock (also GPIO39, CLK_OUT3 and SUBSPICS1), powered from VDD3P3_CPU with input enabled. |
| 45 | MTDO | bidirectional | JTAG test data output (also GPIO40 and CLK_OUT2), powered from VDD3P3_CPU. |
| 46 | VDD3P3_CPU | power_in | Digital power domain supply, recommended 3.0 V to 3.6 V with 3.3 V typical; the datasheet says it must not exceed 3.3 V when writing eFuse. |
| 47 | MTDI | bidirectional | JTAG test data input (also GPIO41 and CLK_OUT1), powered from VDD3P3_CPU. |
| 48 | MTMS | bidirectional | JTAG test mode select (also GPIO42), powered from VDD3P3_CPU. |
| 49 | U0TXD | bidirectional | UART0 transmit (also GPIO43 and CLK_OUT1), powered from VDD3P3_CPU with a default weak pull-up. |
| 50 | U0RXD | bidirectional | UART0 receive (also GPIO44 and CLK_OUT2), powered from VDD3P3_CPU with a default weak pull-up. |
| 51 | GPIO45 | bidirectional | General-purpose I/O and strapping pin that sets the VDD_SPI voltage, with a default weak pull-down. |
| 52 | GPIO46 | bidirectional | General-purpose I/O and strapping pin that works with GPIO0 for boot mode and controls ROM log printing, with a default weak pull-down. |
| 53 | XTAL_N | passive | Negative side of the external clock input/output for an active or passive crystal. |
| 54 | XTAL_P | passive | Positive side of the external clock input/output for an active or passive crystal. |
| 55 | VDDA | power_in | Analog power domain supply, recommended 3.0 V to 3.6 V with 3.3 V typical. |
| 56 | VDDA | power_in | Analog power domain supply, recommended 3.0 V to 3.6 V with 3.3 V typical. |
| 57 | GND | power_in | Ground, connected to the exposed pad of the QFN56 package. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Espressif Systems |
| Package | QFN-56-EP(7x7) |
| Category | RF And Wireless |
| Pins | 57 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Allowable input voltage (power supply pins) | | -0.3 | | 3.6 | V | | 60 |
| IO output total current | Ioutput | | | 1500 | mA | | 60 |
| Storage temperature | TSTORE | -40 | | 150 | °C | | 60 |
| Recommended input voltage (VDDA, VDD3P3) | VDDA, VDD3P3 | 3 | 3.3 | 3.6 | V | | 60 |
| Recommended input voltage (VDD3P3_RTC) | VDD3P3_RTC | 3 | 3.3 | 3.6 | V | | 60 |
| Recommended input voltage (VDD_SPI input) | VDD_SPI | 1.8 | 3.3 | 3.6 | V | | 60 |
| Recommended input voltage (VDD3P3_CPU) | VDD3P3_CPU | 3 | 3.3 | 3.6 | V | | 60 |
| Input total current | IVDD | 0.5 | | | A | 使用单电源供电时 | 60 |
| Low-level input voltage | VIL | -0.3 | | | V | | 61 |
| High-level input current | IIH | | | 50 | nA | | 61 |
| Low-level input current | IIL | | | 50 | nA | | 61 |
| Chip reset voltage (low) | VIL_nRST | -0.3 | | | V | CHIP_PU 应满足电压范围 | 61 |
| DNL (differential nonlinearity) | DNL | -4 | | 4 | LSB | | 62 |
| INL (integral nonlinearity) | INL | -8 | | 8 | LSB | | 62 |
| Sampling speed | | | | 100 | kSPS | | 62 |
| ADC total error (ATTEN0) | | -5 | | 5 | mV | ATTEN0，有效测量范围为 0 ~ 850 | 62 |
| ADC total error (ATTEN1) | | -6 | | 6 | mV | ATTEN1，有效测量范围为 0 ~ 1100 | 62 |
| ADC total error (ATTEN2) | | -10 | | 10 | mV | ATTEN2，有效测量范围为 0 ~ 1600 | 62 |
| ADC total error (ATTEN3) | | -50 | | 50 | mV | ATTEN3，有效测量范围为 0 ~ 2900 | 62 |
| ESD HBM (human body model) | | -2000 | | 2000 | V | HBM, JS-001 | 64 |
| ESD CDM (charged device model) | | -1000 | | 1000 | V | CDM, JS-002 | 64 |
| Latch-up current | | -200 | | 200 | mA | JESD78 过电流 | 64 |
| Wi-Fi operating channel center frequency | | 2412 | | 2484 | MHz | | 65 |
## CAD (KiCad official)
- Symbol: `ESP32-S3`
- Footprint: `Package_DFN_QFN:QFN-56-1EP_7x7mm_P0.4mm_EP4x4mm`
- 3D model: QFN-56-EP(7x7) (KiCad packages3D, STEP)
- 3D model files: `esp32-s3-etched.step` / `esp32-s3-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `esp32-s3.step` / `esp32-s3.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Espressif Systems datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8708768114436325376) (79 pp, sha256 `97b4b3199f87c43f`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/esp32-s3-datasheet.pdf)