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ESP32-S2R2

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Espressif Systems RF and Wireless, 56-VFQFN Exposed Pad. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ESP32-S2R2

Espressif Systems · RF and Wireless · 56-VFQFN Exposed Pad

ESP32-S2R2 from Espressif Systems, in a 56-VFQFN Exposed Pad. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDA power_in Analog power domain supply input for the chip's analog circuitry.
2 LNA_IN bidirectional RF low-noise amplifier input/output signal for the 2.4 GHz receive path.
3 VDD3P3 power_in Analog power domain supply input.
4 VDD3P3 power_in Analog power domain supply input.
5 GPIO0 bidirectional General-purpose I/O (also RTC_GPIO0) and strapping pin for chip boot mode control, with weak pull-up enabled at reset.
6 GPIO1 bidirectional General-purpose I/O also available as RTC_GPIO1, TOUCH1 and ADC1_CH0.
7 GPIO2 bidirectional General-purpose I/O also available as RTC_GPIO2, TOUCH2 and ADC1_CH1.
8 GPIO3 bidirectional General-purpose I/O also available as RTC_GPIO3, TOUCH3 and ADC1_CH2.
9 GPIO4 bidirectional General-purpose I/O also available as RTC_GPIO4, TOUCH4 and ADC1_CH3.
10 GPIO5 bidirectional General-purpose I/O also available as RTC_GPIO5, TOUCH5 and ADC1_CH4.
11 GPIO6 bidirectional General-purpose I/O also available as RTC_GPIO6, TOUCH6 and ADC1_CH5.
12 GPIO7 bidirectional General-purpose I/O also available as RTC_GPIO7, TOUCH7 and ADC1_CH6.
13 GPIO8 bidirectional General-purpose I/O also available as RTC_GPIO8, TOUCH8, ADC1_CH7 and SUBSPICS1.
14 GPIO9 bidirectional General-purpose I/O also available as RTC_GPIO9, TOUCH9, ADC1_CH8, SUBSPIHD and FSPIHD.
15 GPIO10 bidirectional General-purpose I/O also available as RTC_GPIO10, TOUCH10, ADC1_CH9, FSPIIO4, SUBSPICS0 and FSPICS0.
16 GPIO11 bidirectional General-purpose I/O also available as RTC_GPIO11, TOUCH11, ADC2_CH0, FSPIIO5, SUBSPID and FSPID.
17 GPIO12 bidirectional General-purpose I/O also available as RTC_GPIO12, TOUCH12, ADC2_CH1, FSPIIO6, SUBSPICLK and FSPICLK.
18 GPIO13 bidirectional General-purpose I/O also available as RTC_GPIO13, TOUCH13, ADC2_CH2, FSPIIO7, SUBSPIQ and FSPIQ.
19 GPIO14 bidirectional General-purpose I/O also available as RTC_GPIO14, TOUCH14, ADC2_CH3, FSPIDQS, SUBSPIWP and FSPIWP.
20 VDD3P3_RTC power_in RTC domain supply input.
21 XTAL_32K_P bidirectional Positive 32 kHz clock signal connected to the crystal or oscillator, also usable as GPIO15, RTC_GPIO15, U0RTS and ADC2_CH4.
22 XTAL_32K_N bidirectional Negative 32 kHz clock signal for the external 32 kHz crystal or clock input/output, also usable as GPIO16, RTC_GPIO16, U0CTS and ADC2_CH5.
23 DAC_1 bidirectional DAC channel 1 analog voltage output, also usable as GPIO17, RTC_GPIO17, U1TXD and ADC2_CH6.
24 DAC_2 bidirectional DAC channel 2 analog voltage output, also usable as GPIO18, RTC_GPIO18, U1RXD and ADC2_CH7.
25 GPIO19 bidirectional General-purpose I/O also available as RTC_GPIO19, ADC2_CH8, U1RTS and USB_D-, which is connected to USB OTG by default.
26 GPIO20 bidirectional General-purpose I/O also available as RTC_GPIO20, ADC2_CH9, U1CTS and USB_D+, which is connected to USB OTG by default.
27 VDD3P3_RTC_IO power_in RTC and part of digital power domain supply that powers the RTC IO pins.
28 GPIO21 bidirectional General-purpose I/O also available as RTC_GPIO21.
29 SPICS1 bidirectional SPI chip select 1 on the VDD_SPI domain, allocated to in-package PSRAM and not recommended for other uses.
30 VDD_SPI power_out Power pin for the flash/PSRAM SPI IO domain, acting as a backup power line input or as a regulator output to in-package or off-package flash/PSRAM depending on configuration.
31 SPIHD bidirectional SPI hold signal on the VDD_SPI domain, allocated to in-package flash/PSRAM and not recommended for other uses.
32 SPIWP bidirectional SPI write protect signal on the VDD_SPI domain, allocated to in-package flash/PSRAM and not recommended for other uses.
33 SPICS0 bidirectional SPI chip select 0 on the VDD_SPI domain, allocated to in-package flash and not recommended for other uses.
34 SPICLK bidirectional SPI clock on the VDD_SPI domain, allocated to in-package flash/PSRAM and not recommended for other uses.
35 SPIQ bidirectional SPI data line (MISO) on the VDD_SPI domain, allocated to in-package flash/PSRAM and not recommended for other uses.
36 SPID bidirectional SPI data line (MOSI) on the VDD_SPI domain, allocated to in-package flash/PSRAM and not recommended for other uses.
37 GPIO33 bidirectional General-purpose I/O on the VDD_SPI/VDD3P3_CPU domain, used as the high data line IO4 in 8-line SPI mode.
38 GPIO34 bidirectional General-purpose I/O on the VDD_SPI/VDD3P3_CPU domain, used as the high data line IO5 in 8-line SPI mode.
39 GPIO35 bidirectional General-purpose I/O on the VDD_SPI/VDD3P3_CPU domain, used as the high data line IO6 in 8-line SPI mode.
40 GPIO36 bidirectional General-purpose I/O on the VDD_SPI/VDD3P3_CPU domain, used as the high data line IO7 in 8-line SPI mode.
41 GPIO37 bidirectional General-purpose I/O on the VDD_SPI/VDD3P3_CPU domain, used as the DQS signal in 8-line SPI mode.
42 GPIO38 bidirectional General-purpose I/O on the VDD3P3_CPU digital domain.
43 MTCK bidirectional JTAG test clock, also usable as GPIO39; input enabled.
44 MTDO bidirectional JTAG test data output, also usable as GPIO40.
45 VDD3P3_CPU power_in Digital power domain supply input for digital IO.
46 MTDI bidirectional JTAG test data input, also usable as GPIO41; input enabled.
47 MTMS bidirectional JTAG test mode select, also usable as GPIO42; input enabled.
48 U0TXD bidirectional UART0 transmit data, also usable as GPIO43; weak pull-up enabled at reset.
49 U0RXD bidirectional UART0 receive data, also usable as GPIO44; weak pull-up enabled at reset.
50 GPIO45 bidirectional General-purpose I/O and strapping pin for VDD_SPI voltage selection, with weak pull-down enabled at reset.
51 VDDA power_in Analog power domain supply input.
52 XTAL_N passive External clock input/output connected to the oscillator (negative side of the differential clock).
53 XTAL_P passive External clock input/output connected to the oscillator (positive side of the differential clock).
54 VDDA power_in Analog power domain supply input.
55 GPIO46 input Input-only GPIO46 strapping pin with fixed pull-down, used for chip boot mode and ROM message printing control.
56 CHIP_PU input Power-up and reset pin: high starts the chip and low shuts it down; it must not be left floating.
57 GND power_in External ground connection to the exposed pad.

Key specifications

Parameter Value
Manufacturer Espressif Systems
Package 56-VFQFN Exposed Pad
Category RF and Wireless
Pins 57

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Allowed input voltage -0.3 3.6 V Input power pins 48
Cumulative IO output current 1800 mA 48
Storage temperature TSTORE -40 150 °C 48
Recommended input voltage VDDA, VDD3P3, VDD3P3_RTC 2.8 3.3 3.6 V 48
Recommended input voltage VDD3P3_RTC_IO 3 3.3 3.6 V 48
Recommended input voltage VDD_SPI 1.8 3.3 3.6 V As input 48
Cumulative input current IVDD 0.5 A 48
Junction temperature TJ -40 125 °C 48
Temperature sensor range -20 110 °C 45
High-level input current IIH 50 nA 49
Low-level input current IIL 50 nA 49
Differential nonlinearity DNL -7 7 LSB External 100 nF capacitor on ADC; DC signal input; 25 °C; Wi-Fi off 50
Integral nonlinearity INL -12 12 LSB External 100 nF capacitor on ADC; DC signal input; 25 °C; Wi-Fi off 50
Sampling rate 100 kSPS 50
ADC total error -10 10 mV ATTEN0, effective measurement range of 0 ~ 700 50
ADC total error -11 11 mV ATTEN1, effective measurement range of 0 ~ 950 50
ADC total error -13 13 mV ATTEN2, effective measurement range of 0 ~ 1200 50
ADC total error -17 17 mV ATTEN3, effective measurement range of 0 ~ 2300 50
Center frequency of operating channel 2412 2484 MHz 54
Time reserved for power rails to stabilize before CHIP_PU is pulled high tSTBL 50 µs VDDA, VDD3P3, VDD3P3_RTC, VDD3P3_RTC_IO, VDD3P3_CPU 27
Time reserved for CHIP_PU to stay below VIL_nRST to reset the chip tRST 50 µs 27
Pin capacitance CIN 2 pF 49
High-level source current IOH 40 mA VDD = 3.3 V, VOH >= 2.64 V, PAD_DRIVER = 3 49
Low-level sink current IOL 28 mA VDD = 3.3 V, VOL = 0.495 V, PAD_DRIVER = 3 49
Internal weak pull-up resistor RPU 45 kΩ 49
Internal weak pull-down resistor RPD 45 kΩ 49
VDD_SPI internal resistance RSPI RSPI 5 Ω VDD_SPI powered by VDD3P3_RTC via RSPI for 3.3 V flash/PSRAM 49
VDD_SPI output current ISPI 40 mA VDD_SPI powered by Flash Voltage Regulator for 1.8 V flash/PSRAM 49

CAD (KiCad official)

  • Symbol: ESP32-S2R2
  • Footprint: Package_DFN_QFN:QFN-56-1EP_7x7mm_P0.4mm_EP5.6x5.6mm
  • 3D model: 56-VFQFN Exposed Pad (KiCad packages3D, STEP)
  • 3D model files: esp32-s2r2-etched.step / esp32-s2r2-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); esp32-s2r2.step / esp32-s2r2.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Espressif Systems datasheet (65 pp, sha256 7c0c54f11e79cc77, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF