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ESP32-S2FN4R2
Public Made by Adomby adom
Espressif Systems WiFi Modules, QFN-56-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownESP32-S2FN4R2
Espressif Systems · WiFi Modules · QFN-56-EP(7x7)
ESP32-S2FN4R2 from Espressif Systems, in a QFN-56-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDDA | power_in | Analog power domain supply pin for the RF and analog circuitry. |
| 2 | LNA_IN | bidirectional | Low Noise Amplifier (RF LNA) input/output signal pin for the 2.4 GHz receive path. |
| 3 | VDD3P3 | power_in | Analog power domain supply pin. |
| 4 | VDD3P3 | power_in | Analog power domain supply pin. |
| 5 | GPIO0 | bidirectional | Strapping pin for chip boot mode with a weak pull-up at reset, configurable via software IO MUX and GPIO matrix functions. |
| 6 | GPIO1 | bidirectional | General-purpose I/O with RTC_GPIO1, TOUCH1 and ADC1_CH0 analog functions, default drive strength 20 mA. |
| 7 | GPIO2 | bidirectional | General-purpose I/O with RTC_GPIO2, TOUCH2 and ADC1_CH1 analog functions, default drive strength 20 mA. |
| 8 | GPIO3 | bidirectional | General-purpose I/O with RTC_GPIO3, TOUCH3 and ADC1_CH2 analog functions, default drive strength 20 mA. |
| 9 | GPIO4 | bidirectional | General-purpose I/O with RTC_GPIO4, TOUCH4 and ADC1_CH3 analog functions, default drive strength 20 mA. |
| 10 | GPIO5 | bidirectional | General-purpose I/O with RTC_GPIO5, TOUCH5 and ADC1_CH4 analog functions, default drive strength 20 mA. |
| 11 | GPIO6 | bidirectional | General-purpose I/O with RTC_GPIO6, TOUCH6 and ADC1_CH5 analog functions, default drive strength 20 mA. |
| 12 | GPIO7 | bidirectional | General-purpose I/O with RTC_GPIO7, TOUCH7 and ADC1_CH6 analog functions, default drive strength 20 mA. |
| 13 | GPIO8 | bidirectional | General-purpose I/O with RTC_GPIO8, TOUCH8 and ADC1_CH7 analog functions, default drive strength 20 mA. |
| 14 | GPIO9 | bidirectional | General-purpose I/O with RTC_GPIO9, TOUCH9 and ADC1_CH8 analog functions, default drive strength 20 mA. |
| 15 | GPIO10 | bidirectional | General-purpose I/O with RTC_GPIO10, TOUCH10 and ADC1_CH9 analog functions, default drive strength 20 mA. |
| 16 | GPIO11 | bidirectional | General-purpose I/O with RTC_GPIO11, TOUCH11 and ADC2_CH0 analog functions, default drive strength 20 mA. |
| 17 | GPIO12 | bidirectional | General-purpose I/O with RTC_GPIO12, TOUCH12 and ADC2_CH1 analog functions, default drive strength 20 mA. |
| 18 | GPIO13 | bidirectional | General-purpose I/O with RTC_GPIO13, TOUCH13 and ADC2_CH2 analog functions, default drive strength 20 mA. |
| 19 | GPIO14 | bidirectional | General-purpose I/O with RTC_GPIO14, TOUCH14 and ADC2_CH3 analog functions, default drive strength 20 mA. |
| 20 | VDD3P3_RTC | power_in | RTC domain supply pin. |
| 21 | XTAL_32K_P | bidirectional | Positive clock signal connected to the crystal or oscillator for the 32 kHz external clock, also usable as RTC_GPIO15 and ADC2_CH4. |
| 22 | XTAL_32K_N | bidirectional | Negative clock signal for the 32 kHz external clock input/output, also usable as RTC_GPIO16 and ADC2_CH5. |
| 23 | DAC_1 | bidirectional | Analog output of 8-bit DAC channel 1, also usable as RTC_GPIO17 and ADC2_CH6; the DAC uses VDD3P3_RTC_IO as voltage reference. |
| 24 | DAC_2 | bidirectional | Analog output of 8-bit DAC channel 2, also usable as RTC_GPIO18 and ADC2_CH7; the DAC uses VDD3P3_RTC_IO as voltage reference. |
| 25 | GPIO19 | bidirectional | General-purpose I/O that is also USB_D- for the USB OTG interface, with ADC2_CH8 and RTC_GPIO19 functions. |
| 26 | GPIO20 | bidirectional | General-purpose I/O that is also USB_D+ for the USB OTG interface, with ADC2_CH9 and RTC_GPIO20 functions. |
| 27 | VDD3P3_RTC_IO | power_in | RTC and part of digital power domain supply for RTC IO pins. |
| 28 | GPIO21 | bidirectional | General-purpose I/O with RTC_GPIO21 function. |
| 29 | SPICS1 | bidirectional | SPI chip select 1 for in-package PSRAM; pin allocated to in-package flash/PSRAM and not recommended for other uses. |
| 30 | VDD_SPI | power_in | In-package memory backup power line, which can also be configured as an output supplying in-package and off-package flash/PSRAM SPI IO. |
| 31 | SPIHD | bidirectional | SPI hold signal for in-package flash/PSRAM; pin allocated to in-package memory and not to be used for other purposes. |
| 32 | SPIWP | bidirectional | SPI write protect signal for in-package flash/PSRAM; pin allocated to in-package memory and not to be used for other purposes. |
| 33 | SPICS0 | bidirectional | SPI chip select 0 for in-package flash; pin allocated to in-package memory and not to be used for other purposes. |
| 34 | SPICLK | bidirectional | SPI clock for in-package flash/PSRAM; pin allocated to in-package memory and not to be used for other purposes. |
| 35 | SPIQ | bidirectional | SPI data line (MISO/SIO1) for in-package flash/PSRAM; pin allocated to in-package memory and not to be used for other purposes. |
| 36 | SPID | bidirectional | SPI data line (MOSI/SIO0) for in-package flash/PSRAM; pin allocated to in-package memory and not to be used for other purposes. |
| 37 | GPIO33 | bidirectional | Higher data line IO4 for 8-line SPI, usable as GPIO only if the chip is not connected to flash or PSRAM in 8-line SPI mode; powered by VDD_SPI or VDD3P3_CPU. |
| 38 | GPIO34 | bidirectional | Higher data line IO5 for 8-line SPI, usable as GPIO only if the chip is not connected to flash or PSRAM in 8-line SPI mode; powered by VDD_SPI or VDD3P3_CPU. |
| 39 | GPIO35 | bidirectional | Higher data line IO6 for 8-line SPI, usable as GPIO only if the chip is not connected to flash or PSRAM in 8-line SPI mode; powered by VDD_SPI or VDD3P3_CPU. |
| 40 | GPIO36 | bidirectional | Higher data line IO7 for 8-line SPI, usable as GPIO only if the chip is not connected to flash or PSRAM in 8-line SPI mode; powered by VDD_SPI or VDD3P3_CPU. |
| 41 | GPIO37 | bidirectional | DQS/DM data strobe for 8-line SPI, usable as GPIO only if the chip is not connected to flash or PSRAM in 8-line SPI mode; powered by VDD_SPI or VDD3P3_CPU. |
| 42 | GPIO38 | bidirectional | General-purpose I/O with IO MUX functions F0-F4, powered by VDD3P3_CPU. |
| 43 | MTCK | bidirectional | JTAG test clock input (default function) that can also be used as GPIO39, powered by VDD3P3_CPU. |
| 44 | MTDO | bidirectional | JTAG test data output (default function) that can also be used as GPIO40, powered by VDD3P3_CPU. |
| 45 | VDD3P3_CPU | power_in | Digital power domain supply pin for digital IO. |
| 46 | MTDI | bidirectional | JTAG test data input (default function) that can also be used as GPIO41, powered by VDD3P3_CPU. |
| 47 | MTMS | bidirectional | JTAG test mode select (default function) that can also be used as GPIO42, powered by VDD3P3_CPU. |
| 48 | U0TXD | bidirectional | UART0 transmit data (default function) that can also be used as GPIO43; has weak pull-up enabled at reset, powered by VDD3P3_CPU. |
| 49 | U0RXD | bidirectional | UART0 receive data (default function) that can also be used as GPIO44; has weak pull-up enabled at reset, powered by VDD3P3_CPU. |
| 50 | GPIO45 | bidirectional | Strapping pin for VDD_SPI voltage, with a weak pull-down enabled at reset, powered by VDD3P3_CPU. |
| 51 | VDDA | power_in | Analog power domain supply pin. |
| 52 | XTAL_N | passive | External clock input/output connected to the chip oscillator (negative side of the differential clock). |
| 53 | XTAL_P | passive | External clock input/output connected to the chip oscillator (positive side of the differential clock). |
| 54 | VDDA | power_in | Analog power domain supply pin. |
| 55 | GPIO46 | input | Input-only GPIO and strapping pin with a fixed pull-down, used for chip boot mode and ROM message printing control. |
| 56 | CHIP_PU | input | Power-up and reset pin: High turns the chip on, Low shuts it down; it must not be left floating. |
| 57 | GND | power_in | External ground connection (exposed pad) for the chip. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Espressif Systems |
| Package | QFN-56-EP(7x7) |
| Category | IoT/Communication Modules |
| Pins | 57 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage on power pins | -0.3 | 3.6 | V | Allowed input voltage | 48 | ||
| Cumulative IO output current | Ioutput | 1800 | mA | 48 | |||
| Storage temperature | TSTORE | -40 | 150 | °C | 48 | ||
| Recommended input voltage VDDA, VDD3P3, VDD3P3_RTC | 2.8 | 3.3 | 3.6 | V | Recommended input voltage | 48 | |
| Recommended input voltage VDD3P3_RTC_IO | 3 | 3.3 | 3.6 | V | Recommended input voltage | 48 | |
| Recommended input voltage VDD_SPI (as input) | 1.8 | 3.3 | 3.6 | V | as input | 48 | |
| Recommended input voltage VDD3P3_CPU | 2.8 | 3.3 | 3.6 | V | Recommended input voltage | 48 | |
| Cumulative input current | IVDD | 0.5 | A | 48 | |||
| Junction temperature | TJ | -40 | 125 | °C | 48 | ||
| High-level input current | IIH | 50 | nA | 49 | |||
| Low-level input current | IIL | 50 | nA | 49 | |||
| Differential nonlinearity | DNL | -7 | 7 | LSB | ADC connected to an external 100 nF capacitor; DC signal input; ambient temperature at 25 °C; Wi-Fi off | 50 | |
| Integral nonlinearity | INL | -12 | 12 | LSB | ADC connected to an external 100 nF capacitor; DC signal input; ambient temperature at 25 °C; Wi-Fi off | 50 | |
| Sampling rate | 100 | kSPS | 50 | ||||
| ADC total error ATTEN0 | -10 | 10 | mV | ATTEN0, effective measurement range of 0 ~ 700 | 50 | ||
| ADC total error ATTEN1 | -11 | 11 | mV | ATTEN1, effective measurement range of 0 ~ 950 | 50 | ||
| ADC total error ATTEN2 | -13 | 13 | mV | ATTEN2, effective measurement range of 0 ~ 1200 | 50 | ||
| ADC total error ATTEN3 | -17 | 17 | mV | ATTEN3, effective measurement range of 0 ~ 2300 | 50 | ||
| Flash power supply voltage (1.8 V) | VCC | 1.65 | 1.8 | 2 | V | Power supply voltage (1.8 V) | 52 |
| Flash power supply voltage (3.3 V) | VCC | 2.7 | 3.3 | 3.6 | V | Power supply voltage (3.3 V) | 52 |
| Flash maximum clock frequency | FC | 80 | MHz | 52 | |||
| Flash program/erase cycles | 100000 | cycles | 52 | ||||
| Flash data retention time | TRET | 20 | years | 52 | |||
| ESD HBM (Human Body Model) | -2000 | 2000 | V | HBM (Human Body Mode) | 52 | ||
| ESD CDM (Charge Device Model) | -1000 | 1000 | V | CDM (Charge Device Mode) | 52 | ||
| Latch-up current trigger | -200 | 200 | mA | Current trigger | 52 | ||
| Pin capacitance | CIN | 2 | pF | 49 | |||
| High-level source current | IOH | 40 | mA | VDD = 3.3 V, VOH >= 2.64 V, PAD_DRIVER = 3 | 49 | ||
| Low-level sink current | IOL | 28 | mA | VDD = 3.3 V, VOL = 0.495 V, PAD_DRIVER = 3 | 49 | ||
| Internal weak pull-up resistor | RPU | 45 | kΩ | 49 | |||
| Internal weak pull-down resistor | RPD | 45 | kΩ | 49 | |||
| VDD_SPI internal resistance | RSPI | 5 | Ω | VDD_SPI powered by VDD3P3_RTC via RSPI for 3.3 V flash/PSRAM | 49 | ||
| VDD_SPI output current | ISPI | 40 | mA | Output current when VDD_SPI is powered by Flash Voltage Regulator for 1.8 V flash/PSRAM | 49 | ||
| Wi-Fi TX peak current 802.11b | 310 | mA | 802.11b, 20 MHz, 1 Mbps, @19.5 dBm | 51 | |||
| Wi-Fi TX peak current 802.11g | 220 | mA | 802.11g, 20 MHz, 54 Mbps, @15 dBm | 51 | |||
| Wi-Fi TX peak current 802.11n 20 MHz | 200 | mA | 802.11n, 20 MHz, MCS7, @13 dBm | 51 | |||
| Wi-Fi TX peak current 802.11n 40 MHz | 160 | mA | 802.11n, 40 MHz, MCS7, @13 dBm | 51 | |||
| Wi-Fi RX peak current 802.11b/g/n 20 MHz | 63 | mA | 802.11b/g/n, 20 MHz | 51 | |||
| Wi-Fi RX peak current 802.11n 40 MHz | 68 | mA | 802.11n, 40 MHz | 51 | |||
| Modem-sleep current CPU idle, clocks disabled | 20 | mA | CPU 240 MHz, CPU is idle, all peripherals clocks disabled | 51 | |||
| Modem-sleep current CPU idle, clocks enabled | 28 | mA | CPU 240 MHz, CPU is idle, all peripherals clocks enabled | 51 | |||
| Modem-sleep current CPU running, clocks disabled | 23 | mA | CPU 240 MHz, CPU is running, all peripherals clocks disabled | 51 | |||
| Modem-sleep current CPU running, clocks enabled | 32 | mA | CPU 240 MHz, CPU is running, all peripherals clocks enabled | 51 | |||
| Light-sleep current | 750 | µA | VDD_SPI and Wi-Fi are powered down, and all GPIOs are high-impedance | 51 | |||
| Deep-sleep current ULP-FSM | 170 | µA | ULP co-processor powered on, ULP-FSM | 51 | |||
| Deep-sleep current ULP-RISC-V | 190 | µA | ULP co-processor powered on, ULP-RISC-V | 51 | |||
| Deep-sleep current ULP sensor-monitored pattern | 22 | µA | ULP sensor-monitored pattern | 51 | |||
| Deep-sleep current RTC timer and RTC memory | 25 | µA | RTC timer + RTC memory | 51 | |||
| Deep-sleep current RTC timer only | 20 | µA | RTC timer only | 51 | |||
| Power-off current | 1 | µA | CHIP_PU is set to low level, the chip is powered off | 51 |
CAD (KiCad official)
- Symbol:
ESP32-S2FN4R2 - Footprint:
Package_DFN_QFN:QFN-56-1EP_7x7mm_P0.4mm_EP5.6x5.6mm - 3D model: QFN-56-EP(7x7) (KiCad packages3D, STEP)
- 3D model files:
esp32-s2fn4r2-etched.step/esp32-s2fn4r2-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);esp32-s2fn4r2.step/esp32-s2fn4r2.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Espressif Systems datasheet (65 pp, sha256
7c0c54f11e79cc77, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).